Patents Examined by Zandra Smith
  • Method for manufacturing semiconductor device, semiconductor manufacturing apparatus, and wafer lift pin-hole cleaning jig
    Patent number: 9721910
    Abstract: To shorten a maintenance time of a semiconductor manufacturing apparatus and to improve productivity of a semiconductor manufacturing line. A semiconductor wafer is processed by the semiconductor manufacturing apparatus in which reaction product in the inside of a wafer lift pin hole was removed using a cleaning jig having a return on its tip part.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: August 1, 2017
    Assignee: Renesas Electronics Corporation
    Inventor: Yohei Hamaguchi
  • Methods of forming semiconductor devices including contact holes
    Patent number: 9721808
    Abstract: Methods of fabricating a semiconductor device are provided. The methods may include forming a stopper layer on a target layer including a cell area and an edge area, forming a hard mask including first upper openings and dam trench on the stopper layer, forming opening spacers on inner walls of the first upper openings and a dam pattern in the dam trench, removing the stopper layer exposed in the first upper openings to form first lower openings, forming pillar patterns in the first lower openings and the first upper openings and an eaves pattern on the dam pattern, removing the hard mask in the cell area, forming a first polymer block between the pillar patterns including second upper openings, etching the stopper layer exposed in the second upper openings to form second lower openings, and removing the first polymer block, the pillar patterns, the dam pattern and the eaves pattern.
    Type: Grant
    Filed: February 22, 2016
    Date of Patent: August 1, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dae-Yong Kang, Eunsung Kim, Byungjun Jeon, Joonsoo Park, Soonmok Ha
  • Alignment of three dimensional integrated circuit components
    Patent number: 9721855
    Abstract: A method for aligning a chip onto a substrate is disclosed. The method includes, depositing a ferrofluid, onto a substrate that has one or more pads that electrically couple to a semiconductor layer. The method can include a chip with solder balls electrically coupled to the logic elements of the chip, which can be placed onto the deposited ferrofluid, where the chip is supported on the ferrofluid, in a substantially coplanar orientation to the substrate. The method can include determining if the chip is misaligned from a desired location on the substrate. The method can include adjusting the current location of the chip in response to determining that the solder balls of the chip are misaligned from the desired location on the pads of the substrate, until the chip is aligned in the desired location.
    Type: Grant
    Filed: December 12, 2014
    Date of Patent: August 1, 2017
    Assignee: International Business Machines Corporation
    Inventors: Joseph Kuczynski, Phillip V. Mann, Kevin M. O'Connell, Arvind K. Sinha, Karl Stathakis
  • CMOS ultrasonic transducers and related apparatus and methods
    Patent number: 9718098
    Abstract: CMOS Ultrasonic Transducers and processes for making such devices are described. The processes may include forming cavities on a first wafer and bonding the first wafer to a second wafer. The second wafer may be processed to form a membrane for the cavities. Electrical access to the cavities may be provided.
    Type: Grant
    Filed: May 19, 2016
    Date of Patent: August 1, 2017
    Assignee: Butterfly Network, Inc.
    Inventors: Jonathan M. Rothberg, Keith G. Fife, Tyler S. Ralston, Gregory L. Charvat, Nevada J. Sanchez
  • Double patterning method
    Patent number: 9711372
    Abstract: In some embodiments, the disclosure relates to a method of forming an integrated circuit device. The method is performed by forming a first mask layer over a substrate and a second mask layer over the first mask layer. The second mask layer is patterned to form cut regions. A mandrel is formed over the first mask layer and the cut regions, and the first mask layer is etched using the mandrel form a patterned first mask. The substrate is etched according to the patterned first mask and the cut regions to form trenches in the substrate, and the trenches are filled with conductive metal to form conductive lines.
    Type: Grant
    Filed: November 9, 2015
    Date of Patent: July 18, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Ying Lee, Jyu-Horng Shieh
  • FinFETs with vertical Fins and methods for forming the same
    Patent number: 9711623
    Abstract: In a method for forming a device, a (110) silicon substrate is etched to form first trenches in the (110) silicon substrate, wherein remaining portions of the (110) silicon substrate between the first trenches form silicon strips. The sidewalls of the silicon strips have (111) surface orientations. The first trenches are filled with a dielectric material to from Shallow Trench Isolation (STI) regions. The silicon strips are removed to form second trenches between the STI regions. An epitaxy is performed to grow semiconductor strips in the second trenches. Top portions of the STI regions are recessed, and the top portions of the semiconductor strips between removed top portions of the STI regions form semiconductor fins.
    Type: Grant
    Filed: November 10, 2015
    Date of Patent: July 18, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Ming-Chyi Liu
  • Method for improving mass-production yield of large-area organic solar cells
    Patent number: 9711722
    Abstract: The present invention discloses a method for improving mass-production yield of large-area organic solar cells for forming the active layer using the roll-to-roll process. The active layer includes low-bandgap high-polymer PTB7, Fullerenes derivative PC71BM, and high-boiling-point additives. The addition of the high-boiling-point additives can enhance the efficiency of organic solar cells effectively. In the roll-to-roll process according to the present invention, the drying temperature for the wet film is controlled for controlling the content of additives in the dry film. Thereby, the stability of the overall mass production and the device yield can be both improved.
    Type: Grant
    Filed: December 15, 2015
    Date of Patent: July 18, 2017
    Assignee: Institute of Nuclear Energy Research, Atomic Energy Council, Executive Yuan, R.O.C.
    Inventors: Yu-Ching Huang, Hou-Chin Cha, De-Han Lu, Chih-Min Chuang, Zheng-Lin Yu, Chia-Te Yen, Yeong-Der Lin, Charn-Ying Chen, Cheng-Si Tsao
  • Forming self-aligned conductive lines for resistive random access memories
    Patent number: 9705080
    Abstract: Resistive random access memory elements, such as phase change memory elements, may be defined using a plurality of parallel conductive lines over a stack of layers, at least one of which includes a resistive switching material. The stack may be etched using the conductive lines as a mask. As a result, memory elements may be self-aligned to the conductive lines.
    Type: Grant
    Filed: June 14, 2016
    Date of Patent: July 11, 2017
    Assignee: Mircon Technology, Inc.
    Inventors: Innocenzo Tortorelli, Fabio Pellizzer, Pietro Petruzza
  • Halogenated dopant precursors for epitaxy
    Patent number: 9704708
    Abstract: A method for forming a film on a substrate is provided. The method includes positioning a substrate within a processing volume of a process chamber and heating the substrate. The method further includes forming a semiconductor film on the substrate by exposing the substrate to two or more reactants including a silicon source and a halogenated dopant source. The semiconductor film includes one or more epitaxial regions and one or more non-epitaxial regions.
    Type: Grant
    Filed: July 9, 2015
    Date of Patent: July 11, 2017
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Abhishek Dube, Yihwan Kim, Xuebin Li
  • Electronic devices including organic materials
    Patent number: 9704764
    Abstract: A method comprising forming on a common support (6) one or more series of multi-layer electronic devices (covering the areas 2a, 2b respectively), and then separating the electronic devices; wherein the devices comprise one or more organic layers (9), and the method comprises depositing one or more of the organic layers (9) as a respective continuous layer extending at least from one end of the one or more series of devices to an opposite end of the one or more series of devices.
    Type: Grant
    Filed: October 7, 2014
    Date of Patent: July 11, 2017
    Assignee: FLEXENABLE LIMITED
    Inventor: Bernd Zimmermann
  • Pattern placement error compensation layer
    Patent number: 9704807
    Abstract: A method includes forming a first conductive feature positioned in a first dielectric layer. A conductive polymer layer is formed above the first dielectric layer and the first conductive feature. The conductive polymer layer has a conductive path length. A second dielectric layer is formed above the first dielectric layer. A first via opening is formed in the second dielectric layer and the conductive polymer layer to expose the first conductive feature. A conductive via is formed in the first via opening. The conductive via contacts the first conductive feature and the conductive polymer layer.
    Type: Grant
    Filed: November 12, 2015
    Date of Patent: July 11, 2017
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Deniz E. Civay, Erik R. Hosler
  • On-chip MIM capacitor
    Patent number: 9704856
    Abstract: A method for forming an on-chip capacitor with complementary metal oxide semiconductor (CMOS) devices includes forming a first capacitor electrode between gate structures in a capacitor region while forming contacts to source and drain (S/D) regions in a CMOS region. Gate structures are cut in the CMOS region and the capacitor region by etching a trench across the gate structures and filling the trench with a dielectric material. The gate structures and the dielectric material in the trench in the capacitor region are removed to form a position for an insulator and a second electrode. The insulator is deposited in the position. Gate metal is deposited to form gate conductors in the CMOS region and the second electrode in the capacitor region.
    Type: Grant
    Filed: September 23, 2016
    Date of Patent: July 11, 2017
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Peng Xu
  • Method of dividing wafer into dies
    Patent number: 9704749
    Abstract: A method of dividing a wafer, having on one side a device area with a plurality of devices partitioned by a plurality of division lines and a peripheral marginal area with no devices formed around the device area, into dies is provided. The method comprises: attaching an adhesive tape for protecting devices on the wafer to the one side of the wafer, the adhesive tape adhering to at least some, optionally all, of the devices; connecting a carrier for supporting the adhesive tape to the side of the adhesive tape being opposite to the side in contact with the devices by connecting means; grinding that side of the wafer being opposite the one side for adjusting the wafer height; and cutting the wafer along the division lines. The method is characterized by locating the connecting means completely outward of the device area of the wafer in a top view thereon.
    Type: Grant
    Filed: December 16, 2015
    Date of Patent: July 11, 2017
    Assignee: DISCO CORPORATION
    Inventor: Karl Heinz Priewasser
  • Method for manufacturing solar cell
    Patent number: 9698300
    Abstract: A method of manufacturing a solar cell is discussed. The method of manufacturing the solar cell includes: forming a conductive region on a semiconductor substrate; forming an electrode connected to the conductive region; and post-processing the semiconductor substrate to passivate the semiconductor substrate. The post-processing of the semiconductor substrate comprises a main processing process for heat-treating the semiconductor substrate while providing light to the semiconductor substrate. A temperature of the main processing process is about 100° C. to about 800° C., and the temperature and light intensity of the main processing process satisfy Equation of 1750?31.8·T+(0.16)·T2?I. Here, T is the temperate (° C.) of the main processing process, and I is the light intensity (mW/cm2) of the main processing process.
    Type: Grant
    Filed: June 8, 2015
    Date of Patent: July 4, 2017
    Assignee: LG ELECTRONICS INC.
    Inventors: Kyoungsoo Lee, Minho Choi, Jinhyung Lee, Gyeayoung Kwag, Sangwook Park
  • Semiconductor device and method for manufacturing the same
    Patent number: 9698236
    Abstract: It is made possible to provide a method for manufacturing a semiconductor device that has a high-quality insulating film in which defects are not easily formed, and experiences less leakage current. A method for manufacturing a semiconductor device, includes: forming an amorphous silicon layer on an insulating layer; introducing oxygen into the amorphous silicon layer; and forming a silicon oxynitride layer by nitriding the amorphous silicon layer having oxygen introduced thereinto.
    Type: Grant
    Filed: March 8, 2016
    Date of Patent: July 4, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Daisuke Matsushita, Yuuichiro Mitani
  • Grid array connection device and method
    Patent number: 9698114
    Abstract: A method and device for input/output connections is provided. Devices and methods for connection structure are shown with improved mechanical properties such as hardness and abrasion resistance. Land grid array structures are provided that are less expensive to manufacture due to reductions in material cost such as gold. Ball grid array structures are provided with improved resistance to corrosion during fabrication. Ball grid array structures are also provided with improved mechanical properties resulting in improved shock testing results.
    Type: Grant
    Filed: March 25, 2011
    Date of Patent: July 4, 2017
    Assignee: INTEL CORPORATION
    Inventors: Munehiro Toyama, Siew Fong Tai, Kian Sin Sim, Charan K. Gurumurthy, Selvy Tamil Selvamuniandy
  • Semiconductor device and method of forming the same
    Patent number: 9698059
    Abstract: The present invention provides a semiconductor device and a method of forming the same. The semiconductor device includes a substrate, a first transistor and a second transistor. The first transistor and the second transistor are disposed on the substrate. The first transistor includes a first channel and a first work function layer. The second transistor includes a second channel and a second work function layer, where the first channel and the second channel include different dopants, and the second work function layer and the first work function layer have a same conductive type and different thicknesses.
    Type: Grant
    Filed: April 15, 2015
    Date of Patent: July 4, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Tian Choy Gan, Chu-Yun Hsiao, Chia-Fu Hsu
  • Film transistor array panel and manufacturing method thereof
    Patent number: 9698167
    Abstract: Disclosed is a thin film transistor array panel including: a substrate including a display area and a peripheral area; a second semiconductor layer disposed on the substrate, and disposed on a first semiconductor layer disposed in the display area and the peripheral area; and a passivation layer disposed on the first semiconductor layer and the second semiconductor layer, wherein the first semiconductor layer and the second semiconductor layer include an oxide semiconductor, and a thickness of the first semiconductor layer is different from that of the second semiconductor layer.
    Type: Grant
    Filed: November 6, 2014
    Date of Patent: July 4, 2017
    Assignee: Samsung Display Co., Ltd.
    Inventors: Doo Youl Lee, Hyuk Soon Kwon, Jang Soo Kim
  • Semiconductor structure
    Patent number: 9691754
    Abstract: A semiconductor structure comprises a well, a first lightly doped region, a second lightly doped region, a first heavily doped region, a second heavily doped region and a gate. The first lightly doped region is disposed in the well. The second lightly doped region is disposed in the well and separated from the first lightly doped region. The first heavily doped region is disposed in the first lightly doped region. The second heavily doped region is partially disposed in the second lightly doped region. The second heavily doped region has a surface contacting the well. The gate is disposed on the well between the first heavily doped region and the second heavily doped region. The well has a first doping type. The first lightly doped region, the second lightly doped region, the first heavily doped region and the second heavily doped region have a second doping type.
    Type: Grant
    Filed: April 20, 2015
    Date of Patent: June 27, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Mei-Ling Chao, Yi-Chun Chen, Li-Cih Wang, Tien-Hao Tang
  • Multi-chip fan out package and methods of forming the same
    Patent number: 9691706
    Abstract: A package includes a die having a conductive pad at a top surface of the die, a stud bump over and connected to the conductive pad, and a redistribution line over and connected to the stud bump. An electrical connector is over and electrically coupled to the redistribution line.
    Type: Grant
    Filed: April 20, 2012
    Date of Patent: June 27, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Jing-Cheng Lin, Jui-Pin Hung