Abstract: A voltage regulator comprises first and second bipolar transistors operating at different current densities; a resistance is connected between their bases across which ?VBE appears. A third bipolar transistor is connected such that its base voltage is equal to that of the first transistor or differs by a PTAT amount. A current mirror balances the collector current of one of the second and third transistors with an image of the collector current of the first transistor when an output node is at a unique operating point. The operating point includes both PTAT and CTAT components, the ratio of which can be established to provide a desired temperature characteristic. A feedback transistor provides current to the bases of the bipolar transistors and to the output node and is driven by the current mirror output to regulate the voltage at the output node by negative feedback.

Abstract: A linearized controller to operate a switching power converter which includes an inductor having its first terminal coupled to a first voltage (V1) and its second terminal switched so that it alternately connects to a second, higher voltage (V2) or to a common terminal. A sawtooth voltage generator produces a ramp voltage (Vramp) having a period T and an amplitude which varies in response to a control voltage Vx, and a voltage comparator which compares Vramp to a control voltage Vy. The comparator output controls the switching such that T is divided into intervals t1 and t2, during which the second terminal is connected to the common terminal or to V2, respectively. When Vy is maintained in a fixed proportion to V1, V2 is driven to be in the same proportion to Vx, independently of changes in V1, providing a boost converter. A buck converter is similarly realized.

Abstract: A switching power converter with a controlled startup mechanism includes a switching stage which provides a voltage Vout at an output node in response to a switching control signal, with the output node adapted for connection to a non-linear load. A feedback network compares a signal which varies with the current conducted by the load (Iload) with a reference signal, and provides the switching control signal so as to maintain Iload at a desired value. A capacitor connected to the output node provides a current Ic to the feedback network which varies with dVout/dt. The feedback network is arranged to limit dVout/dt in response to current Ic when Iload is substantially zero. In this way, large inrush currents or damage that might otherwise occur during startup are avoided.

Abstract: A linearized controller to operate a switching power converter which includes an inductor having its first terminal coupled to a first voltage (V1) and its second terminal switched so that it alternately connects to a second, higher voltage (V2) or to a common terminal. A sawtooth voltage generator produces a ramp voltage (Vramp) having a period T and an amplitude which varies in response to a control voltage Vx, and a voltage comparator which compares Vramp to a control voltage Vy. The comparator output controls the switching such that T is divided into intervals t1 and t2, during which the second terminal is connected to the common terminal or to V2, respectively. When Vy is maintained in a fixed proportion to V1, V2 is driven to be in the same proportion to Vx, independently of changes in V1, providing a boost converter. A buck converter is similarly realized.

Abstract: A temperature setpoint circuit comprises bipolar transistors Q1 and Q2 which receive currents I1 and I2 at their respective collectors and are operated at unequal current densities, with a resistance R1 connected between their bases such that the difference in their base-emitter voltages (?Vbe) appears across R1. An additional PTAT current I3 is maintained in a constant ratio to I1 and I2 and provided to the collector of Q2 while Q2 is off, and is not provided while Q2 is on. The circuit is arranged such that Q2 is turned on and conducts a current equal to Ia when: ?Vbe=(kT/q)ln(NI1/Ia), where Ia=I2+I3, the temperature T at which ?Vbe=(kT/q)ln(NI1/Ia) being the circuit's setpoint temperature, such that the switching of current I3 provides hysteresis for the setpoint temperature which is approximately constant over temperature.

Abstract: A differential stage which uses a bias generator circuit to set the operating currents of the input stage FETs to make the incremental Gm primarily a function of a single resistor embedded in the biasing circuit, such that the input stage has a Gm which only gradually departs from nominal under overdrive, and continues to supply output currents which increase with an increasing differential input signal.

Abstract: A semiconductor switch comprises a PNPN structure arranged to provide an SCR-like functionality, and a MOS gate structure, preferably integrated on a common substrate. The switch includes ohmic contacts for the MOS gate, and for the cathode and gate regions of the PNPN structure; the anode contact is intrinsic. A fixed voltage is typically applied to an external node. The MOS gate structure allows current to be conducted between the external node and the intrinsic anode when on, and the PNPN structure conducts the current from the anode to the cathode when an appropriate voltage is applied to the gate contact. Regenerative feedback keeps the switch on once it begins to conduct. The MOS gate inhibits the flow of current between the external node and anode—and thereby turns off the switch—when off. When on, the MOS gate's channel resistance serves as a ballast resistor.

Abstract: A timing circuit operates by applying an arbitrary voltage across a resistance, and using the resulting current to generate a charging current which charges and/or discharges a capacitance to an endpoint voltage. Additional circuitry is arranged such that the capacitance is charged and/or discharged until its voltage crosses a threshold which is proportional to one of the resistance's endpoint voltages, such that the capacitance's endpoint voltage tracks the resistance's endpoint voltage. Thus, the resistor voltage can vary with supply voltage or temperature, or the resistance value itself can vary, without materially affecting the timing relationships. The arbitrary voltage is preferably provided with a pair of diode-connected transistors connected in series with the resistance, so that a single transistor operated at the same current density as one of the diode-connected transistors establishes the threshold voltage and detects when the capacitor voltage reaches the threshold.

Abstract: A small signal amplifier with a large signal output boost stage are connected between first and second supply rails. The small signal amplifier receives first and second input signals and provides an output signal at an output node which drives a load. Under small signal conditions, the output signal varies approximately linearly with the difference voltage. However, under large signal conditions, a rail-to-rail large signal output boost stage connected to the output node is arranged to drive the output node close to the first or second supply rail as needed to provide the current demanded by the load. The large signal output boost stage is off in small signal conditions, but comes on rapidly and transfers maximum charge to the load under large signal conditions.

Abstract: An amplifier output voltage swing extender circuit comprises a differential amplifier powered between first and second power supply rails, which receives first and second input signals at non-inverting and inverting inputs, respectively, and provides an output at a first output node. A level shifting circuit, preferably a voltage divider, is connected in series with the first output node and shifts the node voltage toward the second rail by a fixed amount; the shifted voltage is provided at a second output node. A feedback network couples the second output node voltage to the amplifier's inverting input, such that when a voltage VSET is applied to the non-inverting input, the maximum negative voltage excursion at the first and second output nodes is greater than the value of the VSET voltage with respect to the second supply rail.

Abstract: A curvature corrected bandgap reference circuit comprises a first bipolar transistor having a base-emitter voltage Vbe1 and operated such that it has a constant operating current, and a second bipolar transistor having a base-emitter voltage Vbe2 and operated such that it has an operating current consisting of an approximately temperature proportional component and a non-linear component. The circuit is arranged such that the ratio of the current densities in the two transistors varies with temperature, such that the difference voltage (?Vbe=Vbe1?Vbe2) includes a residual component which approximately compensates bandgap curvature error.

Abstract: A bandgap voltage regulator is arranged such that, when a desired output voltage is present between its output and common terminals, current densities in a pair of bipolar transistors having unequal emitter areas are maintained in a fixed ratio. The difference in the transistors' base-emitter voltages is across a resistor, which thus conducts a PTAT current. The regulator also generates a CTAT current, and both the PTAT and CTAT currents are made to flow in another resistor, with the resulting voltages added by superposition. The regulator's resistors are sized such that Vout is an integral or fractional multiple of Vbg, where Vbg is the bandgap voltage for the fabrication process used to make the regulator's transistors, such that Vout is temperature invariant, to a first order. The resistors are preferably realized using unit resistors having a predetermined resistance, or series and/or parallel combinations of unit resistors.

Abstract: A switched current temperature sensing circuit comprises a BJT arranged to conduct a forced emitter current IE of the form Ifixed+(Ifixed/?), such that the base current is given by Ifixed/? and the collector current is given by Ifixed+(Ifixed/?)?(Ifixed/?)=Ifixed. Base current Ifixed/? is mirrored to the emitter, and a current source provides current Ifixed, which is switched between at least a first value I and a second value N*I such that the BJT's base-emitter voltage has a first value Vbe1 when Ifixed=I and a second value Vbe2 when Ifixed=N*I, such that: ?Vbe12=Vbe1?Vbe2=(nFkT/q)(ln N), where nF is the BJT's emission coefficient, k is Boltzmann's constant, T is absolute temperature, and q is the electron charge.

Abstract: A current mirror circuit includes a current input node for receiving an input current, an upper, cascoded current mirror, a lower current mirror, and a biasing means. In a FET implementation, the upper mirror includes first and second cascoded FETs which are connected together at the current input node, and third and fourth cascoded FETs connected to mirror the current conducted by the first and second FETs. The lower current mirror receives the mirrored current and mirrors it back to the upper mirror, thereby providing positive feedback. The net loop gain is between zero and one. When so arranged, the third and fourth FETs conduct a current which is proportional to an applied input current. The upper mirror transistors are biased such that the voltage at the current input node is substantially closer to the supply voltage than the voltages at the gates of the first and third FETs.

Abstract: A voltage source includes first and second pn junctions which conduct the outputs of respective current sources to establish respective base-emitter voltages Vbe1 and Vbe2 at respective nodes; Vbe1 and Vbe2 can each be generated with a current I or a current N*I. An amplifier A1 has its non-inverting input connected to the second node and its inverting input connected to the first node through an input capacitor; a feedback capacitor is connected between the inverting input and a third node. Switches are connected between A1's inverting input and A1's output, between the third node and A1's output, and between the third node and a circuit common point. A control circuit operates the switches and current sources during first and second operating phases to selectively produce a temperature independent output voltage or a temperature dependent output voltage.

Abstract: A switching voltage converter, suitably a boost converter, employs an n-type transistor, preferably an NMOS FET, as a series switch, with its drain coupled to the cathode of the converter's diode and its source coupled to the converter's output node. A charge pump driven by the converter's switching voltage provides a voltage Von at the NMOS FET's gate input sufficient to turn the FET on. A series switch controller is arranged to, in response to a control signal, hold the NMOS FET off such that the converter's output voltage Vout is approximately zero regardless of the status of input voltage Vin, or allow the NMOS device to be turned on by Von.

Abstract: A high side current monitor circuit includes an op amp which is coupled across a sensing element which carries a current Isense and develops a shunt voltage Vsense. A feedback transistor driven by the op amp output conducts an output current Iout through a resistor to a current output node necessary to make the op amp inputs equal, such that Iout is proportional to Isense. Iout is conducted through a resistor to generate a ground-referred voltage proportional to Vsense. When the common mode voltage of Vsense is greater than the op amp's breakdown voltage, a discrete transistor is connected between the current output node and ground to stand off the voltage across the amp. The monitor circuit is arranged such that it can be powered with a limited fraction of the common mode voltage when used with a discrete transistor, and is self-biased when used without a discrete transistor.

Abstract: A dual voltage switch enables the generation of a pulse which toggles between user-provided first and second voltages (V1 and V2), for which the positive and/or negative slew rates are programmable by means of a user-provided capacitance. A first switch conducts a current I1 between V1 and a common output node in response to a first control voltage, and a second switch conducts a current I2 between V2 and the common output node in response to a second control voltage. A capacitance C is connected to the common output node. A control circuit alternately provides the first and second control voltages such that the common output node is pulled up to V1 at a transfer rate of I1/C when the first control voltage is provided, and pulled down to V2 at a transfer rate of ?I2/C when the second control voltage is provided.

Abstract: A voltage selector circuit determines the highest of at least two available input voltages, and connects the highest voltage to an output terminal. The circuit includes a comparator having first and second FETs having their sources connected to first and second input voltages (V1 and V2), and which are biased with first and second bias currents. The first FET is driven on regeneratively when V1>V2, and the second FET is driven on regeneratively when V2>V1. A first switch connects V1 to an output terminal when the first FET is driven on, and a second switch connects V2 to the output terminal when the second FET is driven on. First and second diode-connected FETs are connected below the first and second FETs and carry their respective bias currents, thereby limiting the voltage swings on the FETs' gates and providing control over hysteresis.

Abstract: A high gain amplifier includes a differential amplifier stage having a pair of transistors; first and second input circuits for providing input signals to the pair of transistors; transistor means arranged as a differential-to-single-ended converter driven by the differential amplifier stage to provide a single ended output signal; an intermediate gain stage having an input responsive to the single ended output signal; bias means for the differential amplifier, the bias means including circuit means for maintaining the currents through the pair of transistors in constant ratio independently of changes in load at the intermediate gain stage; and an inverting gain output stage driven by the intermediate gain stage and having an output for driving a load substantially from rail to rail. Also disclosed is a frequency compensation capacitor circuit connected between the input of the intermediate gain stage and the output of the inverting gain output stage.