Abstract: A media receiver hub receives wireless signals from multiple sources (e.g., satellite signals from multiple satellites) and provides the signals to end devices over a local network. According to an example embodiment, a satellite hub is responsive to channel input selections received from end devices by selecting channels from within received satellite signals, and by converting each channel into a format amenable for delivery to and use at an end device requesting the channel. The converted channels are communicated to the end devices over a network that also facilitates communications between the devices, by restricting the communications to using a portion of the available bandwidth of the network, reserving bandwidth for communications with and/or between the end devices (or other network devices).

Abstract: An erasures assisted block code decoder and related method are provided. The erasures assisted block code decoder includes a first block decoder, an erasures processor, and a second block code decoder. The first block decoder, for example, a Reed-Solomon decoder, is configured to decode blocks of data elements, e.g., bytes, that were previously affected by bursty errors. The first block decoder is also configured to identify those of such blocks it is unable to decode. The erasures processor is configured to identify, as erasures, data elements in the un-decodable blocks by utilizing, in the erasures identification process, data elements in the decoded blocks that were corrected by the first block decoder. The second block decoder, e.g., the same or different Reed-Solomon decoder, is configured to decode one or more of the un-decodable blocks by utilizing, in the decoding, the erasures identified by the erasures processor.

Abstract: A multi-channel decoder system has a decoder core at least a portion of which is configurable as a LDPC decoder that, during decoding processing, divides check nodes of a node representation of a LDPC code into a plurality of groups, and, during an iteration, sequentially processes the groups while processing in parallel the check nodes within each group, thus improving decoding throughput.

Abstract: An erasures assisted block code decoder and related method are provided. The erasures assisted block code decoder comprises a first block decoder, an erasures processor, and a second block code decoder. The first block decoder, for example, a Reed-Solomon decoder, is configured to decode blocks of data elements, e.g., bytes, that were previously affected by bursty errors. The first block decoder is also configured to identify those of such blocks it is unable to decode. The erasures processor is configured to identify, as erasures, data elements in the un-decodable blocks by utilizing, in the erasures identification process, data elements in the decoded blocks that were corrected by the first block decoder. The second block decoder, e.g., the same or different Reed-Solomon decoder, is configured to decode one or more of the un-decodable blocks by utilizing, in the decoding, the erasures identified by the erasures processor.

Abstract: An erasures assisted block code decoder and related method are provided. The erasures assisted block code decoder includes a first block decoder, an erasures processor, and a second block code decoder. The first block decoder, for example, a Reed-Solomon decoder, is configured to decode blocks of data elements, e.g., bytes, that were previously affected by bursty errors. The first block decoder is also configured to identify those of such blocks it is unable to decode. The erasures processor is configured to identify, as erasures, data elements in the un-decodable blocks by utilizing, in the erasures identification process, data elements in the decoded blocks that were corrected by the first block decoder. The second block decoder, e.g., the same or different Reed-Solomon decoder, is configured to decode one or more of the un-decodable blocks by utilizing, in the decoding, the erasures identified by the erasures processor.

Abstract: A known sequence of symbols is located within a transmitted sequence of symbols by estimating the phase differences between offset symbols within a portion or more of the transmitted sequence, estimating the phase differences between offset symbols in the known sequence, and determining that the symbols within the portion or more of the transmitted sequence are the known sequence if the phase difference estimates determined from the symbols within the portion or more of the transmitted sequence are substantially equal to the phase difference estimates determined from the known sequence.

Abstract: A simultaneous multiple channel receiver (“SMCR”) for receiving a combined signal having a plurality of carrier signals, where each carrier signal in the plurality of carriers signals corresponds to a frequency channel, and in response, simultaneously producing a plurality of output data stream signals, is disclosed. The SMCR may include a down-converter front-end capable of receiving the combined signal, a plurality of digital signal processors, wherein each digital signal processor of the plurality of digital signal processors is capable of producing an output data stream signal of the plurality of output data stream signals, and a multi-band filter in signal communication with both the down-converter front-end and the plurality of digital signal processors.

Abstract: A media receiver hub receives wireless signals from multiple sources (e.g., satellite signals from multiple satellites) and provides the signals to end devices over a local network. According to an example embodiment, a satellite hub is responsive to channel input selections received from end devices by selecting channels from within received satellite signals, and by converting each channel into a format amenable for delivery to and use at an end device requesting the channel. The converted channels are communicated to the end devices over a network that also facilitates communications between the devices, by restricting the communications to using a portion of the available bandwidth of the network, reserving bandwidth for communications with and/or between the end devices (or other network devices).

Abstract: Iterative decoder employing multiple external code error checks to lower the error floor and/or improve decoding performance. Data block redundancy, sometimes via a cyclic redundancy check (CRC) or Reed Solomon (RS) code, enables enhanced iterative decoding performance. Improved decoding performance is achieved during interim iterations before the final iteration. A correctly decoded CRC block, indicating a decoded segment is correct with a high degree of certainty, assigns a very high confidence level to the bits in this segment and is fed back to inner and/or outer decoders (with interleaving, when appropriate) for improved iterative decoding. High confidence bits may be scattered throughout inner decoded frames to influence other bit decisions in subsequent iterations. Turbo decoders typically operate relatively well at regions where the BER is high; the invention improves iterative decoder operation at lower BERs, lowering the ‘BER floor’ that is sometimes problematic with conventional turbo decoders.

Abstract: A transcoder is described for converting a received first digital signal with a first modulation and encoding scheme to a second digital signal with a second modulation and encoding scheme. The transcoder may include a demodulator that produces a demodulated digital stream of data from the received first digital signal and a modulator in signal communication with the demodulator, where the modulator modulates the digital stream of data with the second modulation and encoding scheme. Additionally, the transcoder may include an upconverter in signal communication with the modulator, where the upconverter produces the second digital signal.

Abstract: Iterative decoder employing multiple external code error checks to lower the error floor and/or improve decoding performance. Data block redundancy, sometimes via a cyclic redundancy check (CRC) or Reed Solomon (RS) code, enables enhanced iterative decoding performance. Improved decoding performance is achieved during interim iterations before the final iteration. A correctly decoded CRC block, indicating a decoded segment is correct with a high degree of certainty, assigns a very high confidence level to the bits in this segment and is fed back to inner and/or outer decoders (with interleaving, when appropriate) for improved iterative decoding. High confidence bits may be scattered throughout inner decoded frames to influence other bit decisions in subsequent iterations. Turbo decoders typically operate relatively well at regions where the BER is high; the invention improves iterative decoder operation at lower BERs, lowering the ‘BER floor’ that is sometimes problematic with conventional turbo decoders.

Abstract: An exemplary satellite communication system comprises a service provider unit communicably coupled to a number of subscriber units via satellite transmission. The service provider unit includes an encoder configured to encode source data into a serial transmit sequence, and is further capable of supporting at least two modes of operation. The serial transmit sequence includes a first unique word identifying a first mode of operation, and is followed by a first payload packet having a first number of channel symbols corresponding to a source packet encoded in accordance with the first mode of operation identified by the first unique word. The first payload packet is encapsulated by two unique words and the time interval between the two unique words is used to determine the first mode of operation identified by the first unique word.

Abstract: Iterative decoder employing multiple external code error checks to lower the error floor and/or improve decoding performance. Data block redundancy, sometimes via a cyclic redundancy check (CRC) or Reed Solomon (RS) code, enables enhanced iterative decoding performance. Improved decoding performance is achieved during interim iterations before the final iteration. A correctly decoded CRC block, indicating a decoded segment is correct with a high degree of certainty, assigns a very high confidence level to the bits in this segment and is fed back to inner and/or outer decoders (with interleaving, when appropriate) for improved iterative decoding. High confidence bits may be scattered throughout inner decoded frames to influence other bit decisions in subsequent iterations. Turbo decoders typically operate relatively well at regions where the BER is high; the invention improves iterative decoder operation at lower BERs, lowering the ‘BER floor’ that is sometimes problematic with conventional turbo decoders.

Abstract: A method for estimating an SNR-related parameter, such as ES/N0, from one or more symbols. The number of symbols within a predetermined number of symbols that fall within one or more collection areas is counted. The count is then associated with a value of the SNR-related parameter. This association may be performed through one or more lookup tables. In one application, a scaling factor is derived from the count. The scaling factor may be used to scale symbols before they are quantized and inputted into a trellis decoder such as a log-MAP decoder.

Abstract: An erasures assisted block code decoder and related method are provided. The erasures assisted block code decoder comprises a first block decoder, an erasures processor, and a second block code decoder. The first block decoder, for example, a Reed-Solomon decoder, is configured to decode blocks of data elements, e.g., bytes, that were previously affected by bursty errors. The first block decoder is also configured to identify those of such blocks it is unable to decode. The erasures processor is configured to identify, as erasures, data elements in the un-decodable blocks by utilizing, in the erasures identification process, data elements in the decoded blocks that were corrected by the first block decoder. The second block decoder, e.g., the same or different Reed-Solomon decoder, is configured to decode one or more of the un-decodable blocks by utilizing, in the decoding, the erasures identified by the erasures processor.

Abstract: A method and apparatus for processing demodulated data comprising received symbol data is disclosed. A decoder is used to compute estimated symbols and corresponding reliability metrics. The reliability metrics are transformed into reliability weights. Optionally, residuals relating to the difference between the received symbol data and the estimated symbols are computed. Output data are generated comprising any combination of the following: estimated symbols, reliability weights, residuals, and received symbol data. The residuals may be weighted by the reliability metrics and used by demodulation or error compensation loops to instantaneously reduce or increase the bandwidth of these loops.

Abstract: A known sequence of symbols is located within a transmitted sequence of symbols by estimating the phase differences between offset symbols within a portion or more of the transmitted sequence, estimating the phase differences between offset symbols in the known sequence, and determining that the symbols within the portion or more of the transmitted sequence are the known sequence if the phase difference estimates determined from the symbols within the portion or more of the transmitted sequence are substantially equal to the phase difference estimates determined from the known sequence.

Abstract: A multi-channel decoder system has a decoder core, at least a portion of which comprises or is configurable as a LDPC decoder, a plurality of channels to and from the decoder core, and control logic for controlling application of the decoder core to data carried by one or more of the channels.

Abstract: A method and system are described for assigning reliability metrics to error correction coded bits or symbols that are decoded. Survivor and non-survivor paths through a portion of a trellis representation within a sliding window are determined and recorded. Primary and non-primary traceback paths through a portion of the trellis representation are determined from the recorded data. If the primary and non-primary traceback paths diverge at a release point, a reliability metric is assigned to the bit or symbol estimate corresponding to the release point. This metric is derived from the difference between the path metrics of the primary and non-primary traceback paths. Alternately, if the two paths diverge through all or a portion of a release zone, a reliability metric is assigned to the block of bit or symbol estimates corresponding to the portion or more of the release zone where the two paths diverge from one another.

Abstract: A receiver in which sync data detection logic detects unencoded sync data at block boundaries of blocks encoded symbols received over a communications channel. Based on the detection of the sync data, the sync data detection logic determine synchronization information for one or more components of the receiver. It may also determine one or more system parameters by counting the number of symbols between successive instances of the sync data.