Abstract: A simultaneous multiple channel receiver (“SMCR”) for receiving a combined signal having a plurality of carrier signals, where each carrier signal in the plurality of carriers signals corresponds to a frequency channel, and in response, simultaneously producing a plurality of output data stream signals, is disclosed. The SMCR may include a down-converter front-end capable of receiving the combined signal, a plurality of digital signal processors, wherein each digital signal processor of the plurality of digital signal processors is capable of producing an output data stream signal of the plurality of output data stream signals, and a multi-band filter in signal communication with both the down-converter front-end and the plurality of digital signal processors.

Abstract: An iterative system for performing carrier phase tracking of symbols using a serial turbo decoder. Estimates of a buffered block of symbols are provided by a serial turbo decoder. Optionally, reliability metrics for the estimates are provided as well. Responsive to this information, a tracking loop module determines derotation phases for each of the symbols in the buffer. A symbol derotator derotates each of the buffered symbols in the block by its corresponding derotation phase. The derotated symbols are stored back in the buffer. The process may repeat itself for a prescribed number of iterations, after which the serial turbo decoder provides estimates of the underlying source bits.

Abstract: A receiver in which sync data detection logic detects unencoded sync data at block boundaries of blocks encoded symbols received over a communications channel. Based on the detection of the sync data, the sync data detection logic determine synchronization information for one or more components of the receiver. It may also determine one or more system parameters by counting the number of symbols between successive instances of the sync data.

Abstract: Iterative decoder employing multiple external code error checks to lower the error floor and/or improve decoding performance. Data block redundancy, sometimes via a cyclic redundancy check (CRC) or Reed Solomon (RS) code, enables enhanced iterative decoding performance. Improved decoding performance is achieved during interim iterations before the final iteration. A correctly decoded CRC block, indicating a decoded segment is correct with a high degree of certainty, assigns a very high confidence level to the bits in this segment and is fed back to inner and/or outer decoders (with interleaving, when appropriate) for improved iterative decoding. High confidence bits may be scattered throughout inner decoded frames to influence other bit decisions in subsequent iterations.

Abstract: Iterative decoder employing multiple external code error checks to lower the error floor and/or improve decoding performance. Data block redundancy, sometimes via a cyclic redundancy check (CRC) or Reed Solomon (RS) code, enables enhanced iterative decoding performance. Improved decoding performance is achieved during interim iterations before the final iteration. A correctly decoded CRC block, indicating a decoded segment is correct with a high degree of certainty, assigns a very high confidence level to the bits in this segment and is fed back to inner and/or outer decoders (with interleaving, when appropriate) for improved iterative decoding. High confidence bits may be scattered throughout inner decoded frames to influence other bit decisions in subsequent iterations.

Abstract: A system for carrier phase tracking of symbols. In an embodiment employing a feedback structure, a symbol derotator pre-rotates a symbol by a derotation phase. A symbol and reliability estimation engine provides, responsive to the pre-rotated symbol, an estimate of the symbol and a reliability metric for the estimate. A tracking loop module determines a residual between the pre-rotated symbol and the symbol estimate, weights the residual by the reliability metric for the estimate, and determines a phase offset estimate responsive to the weighted residual. An accumulator then determines a next derotation phase responsive to the phase offset estimate. In an embodiment employing a feedforward structure, a symbol and reliability estimation engine provides an estimate of a symbol and a reliability metric for the estimate.

Abstract: A receiver in which sync data detection logic detects unencoded sync data at block boundaries of blocks encoded symbols received over a communications channel. Based on the detection of the sync data, the sync data detection logic determine synchronization information for one or more components of the receiver. It may also determine one or more system parameters by counting the number of symbols between successive instances of the sync data.

Abstract: A method and apparatus for processing demodulated data comprising received symbol data is disclosed. A decoder is used to compute estimated symbols and corresponding reliability metrics. The reliability metrics are transformed into reliability weights. Optionally, residuals relating to the difference between the received symbol data and the estimated symbols are computed. Output data are generated comprising any combination of the following: estimated symbols, reliability weights, residuals, and received symbol data. The residuals may be weighted by the reliability metrics and used by demodulation or error compensation loops to instantaneously reduce or increase the bandwidth of these loops.

Abstract: A decoder having a first decoder providing first decoded data. A deinterleaver is included for deinterleaving the first decoded data. A second decoder provides second decoded data based on the deinterleaved first decoded data. The second decoder provides at least one decode status signal indicative of second decoder operations. A pipeline decoder unit is included that is coupled to the second decoder. The pipeline decoder unit includes an encoder that receives the second decoded data and provides forced decision data, a multiplexer, and a third decoder that provides pipelined decoded data. The multiplexer is responsive to the at least one decode status signal to selectively constrain the pipelined decoded data to be at least partially dependent on the forced decision data.

Abstract: An iterative system for performing carrier phase tracking of symbols using a serial turbo decoder. Estimates of a buffered block of symbols are provided by a serial turbo decoder. Optionally, reliability metrics for the estimates are provided as well. Responsive to this information, a tracking loop module determines derotation phases for each of the symbols in the buffer. A symbol derotator derotates each of the buffered symbols in the block by its corresponding derotation phase. The derotated symbols are stored back in the buffer. The process may repeat itself for a prescribed number of iterations, after which the serial turbo decoder provides estimates of the underlying source bits.

Abstract: A rate n/n recursive, systematic encoder. In combination with a bit to symbol mapper, the encoder advantageously forms an inner encoder of a serial concatenated trellis coded modulation encoder. The encoder may also form the inner encoder of a serial concatenated convolutional encoder. A related decoder is also described.

Abstract: Iterative decoder employing multiple external code error checks to lower the error floor and/or improve decoding performance. Data block redundancy, sometimes via a cyclic redundancy check (CRC) or Reed Solomon (RS) code, enables enhanced iterative decoding performance. Improved decoding performance is achieved during interim iterations before the final iteration. A correctly decoded CRC block, indicating a decoded segment is correct with a high degree of certainty, assigns a very high confidence level to the bits in this segment and is fed back to inner and/or outer decoders (with interleaving, when appropriate) for improved iterative decoding. High confidence bits may be scattered throughout inner decoded frames to influence other bit decisions in subsequent iterations.

Abstract: The present invention provides an apparatus and method for signal recovery from noisy observation in digital communication systems, utilizing a forward estimator and data smoother which improves the quality of the estimates of the transmitted signal. The present invention also provides an apparatus and method for the application of the forward estimator to the recovery of a digital data stream modulated with a CPM waveform, through the use of a receiver for GMSK demodulation. The digital data is first processed using the Forward Estimation process which calculates the probability that a symbol is in particular states. Bit decision is then applied, followed by scaling. The present invention further provides an apparatus and method for the application of the forward estimator and data smoother to the decoding of digital data which has been encoded with a Convolutional code. The digital data is first processed using the Forward Estimation procedure and then smoothed and scaled. Bit decision is then applied.