Abstract: Techniques for emulating a configuration space by a peripheral device may include receiving a access request, determining that the access request is for an emulated configuration space of the peripheral device, and retrieving an emulated configuration from an emulated configuration space. The access request can then be serviced by using the emulated configuration.

Abstract: A method for writing data, the method may include: receiving or generating, by an interfacing module, a data unit coherent write request for performing a coherent write operation of a data unit to a first address; receiving, by the interfacing module and from a circuit that comprises a cache and a cache controller, a cache coherency indicator that indicates that a most updated version of the content stored at the first address is stored in the cache; and instructing, by the interfacing module, the cache controller to invalidate a cache line of the cache that stored the most updated version of the first address without sending the most updated version of the content stored at the first address from the cache to a memory module that differs from the cache if a length of the data unit equals a length of the cache line.

Abstract: Provided are systems and methods for generating transactions with a configurable port. In some implementations, a peripheral device is provided. The peripheral device comprises a configurable port. In some implementations, the configurable port may be configured to receive a first transaction. In these implementations, the first transactions may include an address. The address may include a transaction attribute. In some implementations, the configurable port may extract the transaction attribute and a transaction address from the address. The configurable port may further generate a second transaction that includes the transaction attribute and the transaction address. The configurable port may also transmit the second transaction.

Abstract: Apparatus, methods, and computer-readable storage media are disclosed for core-to-core communication between physical and/or virtual processor cores. In some examples of the disclosed technology, application cores write notification data (e.g., to doorbell or PCI configuration memory space accesses via a memory interface), without synchronizing with the other application cores or the service cores. In one examples of the disclosed technology, a message selection circuit is configured to, serialize data from the plurality of user cores by: receiving data from a user core, selecting one of the service cores to send the data based on a memory location addressed by the sending user core, and sending the received data to a respective message buffer dedicated to the selected service core.

Abstract: Techniques for emulating a configuration space by a peripheral device may include receiving a configuration access request, determining that the configuration access request is for a configuration space other than a native configuration space of the peripheral device, and retrieving an emulated configuration from an emulated configuration space. The configuration access request can then be serviced by using the emulated configuration.

Abstract: A method for writing data, the method may include: receiving or generating, by an interfacing module, a data unit coherent write request for performing a coherent write operation of a data unit to a first address; receiving, by the interfacing module and from a circuit that comprises a cache and a cache controller, a cache coherency indicator that indicates that a most updated version of the content stored at the first address is stored in the cache; and instructing, by the interfacing module, the cache controller to invalidate a cache line of the cache that stored the most updated version of the first address without sending the most updated version of the content stored at the first address from the cache to a memory module that differs from the cache if a length of the data unit equals a length of the cache line.

Abstract: Provided are systems and methods for hot-plugging emulated peripheral devices (e.g., endpoints) into host devices that either have a hypervisor that does not support virtualized peripheral device or that do not include a hypervisor. In various implementations, a configurable peripheral device can emulate a switch that includes upstream ports and downstream ports. When a new endpoint device is requested, the configurable peripheral device can, using an emulation configuration for the new endpoint device, generate an emulation for the new endpoint device. The configurable peripheral device can connect the endpoint device to a downstream port, and then trigger a hot-plug mechanism, through which the host device can add the new endpoint device to the known hardware of the host device.

Abstract: Disclosed herein is a distributed performance monitor circuit that includes a plurality of performance monitors connected to a cross-trigger network. Each performance monitor corresponds to a respective functional block of a system and includes a counter circuit. The counter circuit includes a programmable time window counter configured to determine an adjustable counting period, and an event counter configured to count a number of occurrences of an event occurring in the respective functional block during the counting period. The cross-trigger network is configured to receive an output trigger signal generated by a performance monitor when the number of occurrences of the event occurring in the corresponding functional block during the counting period is outside of a threshold band for the performance monitor, and send an input trigger signal to the plurality of performance monitors based on receiving the output trigger signal.

Abstract: An emulated input/output memory management unit (IOMMU) includes a management processor to perform page table translation in software. The emulated IOMMU can also include a hardware input/output translation lookaside buffer (IOTLB) to store translations between virtual addresses and physical memory addresses. When a translation from a virtual address to a physical address is not found in the IOTLB for an I/O request, the translation can be generated by the management processor using page tables from a memory and can be stored in the IOTLB. Some embodiments can be used to emulate interrupt translation service for message based interrupts for an interrupt controller.

Abstract: Apparatus, methods, and computer-readable storage media are disclosed for core-to-core communication between physical and/or virtual processor cores. In some examples of the disclosed technology, application cores write notification data (e.g., to doorbell or PCI configuration memory space accesses via a memory interface), without synchronizing with the other application cores or the service cores. In one examples of the disclosed technology, a message selection circuit is configured to, serialize data from the plurality of user cores by: receiving data from a user core, selecting one of the service cores to send the data based on a memory location addressed by the sending user core, and sending the received data to a respective message buffer dedicated to the selected service core.

Abstract: A processor in a peripheral device can include a wait-for-event mechanism, through which the processor can enter low-power mode and be woken from lower-power mode with an event. Using an event, rather than an interrupt, allows the processor to wake without the latency incurred by an interrupt handling routine. In various implementations, the processor may be configured to execute a sequence of instructions that include a wait-for-event instruction. The wait-for-event instruction can be called when the processor is idle. The wait-for-event instruction may initiate a low-power mode for the processor, wherein the processor suspends executing the sequence of instructions. The processor may further be configured to receive, at an event input, an event signal. The event signal may cause the processor to exit the low-power mode and to resume executing the sequence of instructions from the point at which the processor suspended executing the sequence of instructions.

Abstract: Efficient memory management can be provided in a multi-tenant virtualized environment by encrypting data to be written in memory by a virtual machine using a cryptographic key specific to the virtual machine. Encrypting data associated with multiple virtual machines using a cryptographic key unique to each virtual machine can minimize exposure of the data stored in the memory shared by the multiple virtual machines. Thus, some embodiments can eliminate write cycles to the memory that are generally used to initialize the memory before a virtual machine can write data to the memory if the memory was used previously by another virtual machine.

Abstract: A peripheral device may implement alternative reporting of errors and other events detected at the peripheral device. A peripheral device may monitor the operations of the peripheral device for reporting events. Upon detecting a reporting event, a notification of the reporting event may be generated and sent to a remote data store. The remote data store may store the reporting event and evaluate the reporting event for a responsive action that may be performed. If a responsive action is determined, then the remote data store may direct the performance of the responsive action. The remote data store may provide access to stored reporting events for a peripheral device.

Abstract: A hybrid approach using hardware and software is used for report management in peripheral component interconnect (PCI) express devices. The device hardware detects an error associated with a transaction with a host computer. The device software identifies a function associated with the error and determines various attributes of the error. The device software then exposes the attributes of the error in the PCI express and the advanced error reporting (AER) capabilities. The error can be reported in a message transaction to the host computer.

Abstract: A plurality of system on chips (SoCs) in a server computer can be coupled to a plurality of memory agents (MAs) via respective Serializer/Deserializer (SerDes) interfaces. Each of the plurality of MAs can include one or more memory controllers to communicate with a memory coupled to the respective MA, and globally addressable by each of the SoCs. Each of the plurality of SoCs can access the memory coupled to any of the MAs in uniform number of hops using the respective SerDes interfaces. Different types of memories, e.g., volatile memory, persistent memory, can be supported.

Abstract: Disclosed herein are techniques for migrating data from a source memory range to a destination memory while data is being written into the source memory range. An apparatus includes a control logic configured to receive a request for data migration and initiate the data migration using a direct memory access (DMA) controller, while the source memory range continues to accept write operations. The apparatus also includes a tracking logic coupled to the control logic and configured to track write operations performed to the source memory range while data is being copied from the source memory range to the destination memory. The control logic is further configured to initiate copying data associated with the tracked write operations to the destination memory.

Abstract: Provided are systems and methods for detecting excessive use of a peripheral device by host processes. In various implementations, a peripheral device can include an integrated circuit that includes a traffic counter. The traffic counter can increment based on events received by the peripheral device. The peripheral device can further include an integrated circuit device configured to associate the traffic counter with a process executing on a host device. The integrated circuit device can further initialize a rate counter for the process. When the rate counter reaches a pre-determined time limit, the integrated circuit device can determine that the process is exceeding a usage limit. The integrated circuit device can further read a value from the traffic counter to verify usage of the peripheral device by the process.

Abstract: Provided are methods and adapter devices for buffering write transactions directed to a large space. In various implementations, an adapter device may include a sequential address buffer and a memory. A region of the memory may be configured as a data block, which may be associated with an address range. The address range may correspond to a region of an address space of a target device. The adapter device may be configured to receive a write transaction, the write transaction having an address and data. The adapter device may further write the address to the sequential address buffer. The adapter device may further determine that the address is within the address range, and to write the data to the data block. The adapter device may further, upon the occurrence of an event, write the data from the data block to the region of the address space of the target device.

Abstract: A master device transmits a transaction to a target device. The transaction includes a transaction identifier. An ordering message is sent to the target device over a bus that is different than a communication channel that the transaction is transmitted over. The ordering message includes the transaction identifier. The target device adjusts an order of execution of the transaction by the target device based at least in part on receiving the ordering message.

Abstract: A method of transferring data between a host and a PCI device is disclosed. The method comprises mapping a fixed memory-mapping control block in a host memory of the host to a control register of a memory-mapping unit of the PCI device; mapping a dynamic data-access memory block in the host memory to a default memory block in a memory of the PCI device, wherein the memory-mapping unit translates an address between the dynamic data-access memory block and a memory block in the memory of the PCI device; and dynamically modifying a value in the control register of the memory-mapping unit through the fixed memory-mapping control block such that an address of the dynamic data-access memory block in the host memory is translated to a different address in the memory of the PCI device based on the modified value in the control register of the memory-mapping unit.