Abstract: A network device stores information associated with a packet in a queue. The network device sends an interrupt to a host to notify the host of completion of processing the packet. A Memory-Mapped Input/Output (MMIO) write transaction is received that includes a pointer update associated with the queue and an interrupt unmasking value. The pointer is updated and the interrupt is unmasked based on receiving the single MMIO write transaction.

Abstract: Disclosed herein is a performance monitor for a functional block of a system, the performance monitor comprising a counter circuit, wherein the counter circuit includes a programmable time window counter configured to determine an adjustable counting period, and an event counter coupled to the time window counter. The event counter is configured to count a number of occurrences of an event occurring in the functional block during the counting period, and record the number of occurrences of the event during the counting period and generate an output trigger signal when the number of occurrences of the event during the counting period is outside of a programmable threshold band, or after receiving an input trigger signal from a cross trigger network triggered by other performance monitors in electrical communication with the cross trigger network.

Abstract: A method for writing data, the method may include: receiving or generating, by an interfacing module, a data unit coherent write request for performing a coherent write operation of a data unit to a first address; receiving, by the interfacing module and from a circuit that comprises a cache and a cache controller, a cache coherency indicator that indicates that a most updated version of the content stored at the first address is stored in the cache; and instructing, by the interfacing module, the cache controller to invalidate a cache line of the cache that stored the most updated version of the first address without sending the most updated version of the content stored at the first address from the cache to a memory module that differs from the cache if a length of the data unit equals a length of the cache line.

Abstract: Provided are methods and peripheral devices for examining local hardware and configuring a location-aware peripheral device accordingly. In some implementations, a peripheral device may be configured to examine, using a bus interface, another device connected to the bus. Examining may include determining characteristics of the other device. In some implementations, the peripheral device may further compare the determined characteristics against information derived from data stored in a memory of the peripheral device. The information may describe acceptable operating parameters for the computing system. In some implementations, the peripheral device may further determine, based on a result of the comparison, a status for the computing system. The status may indicate whether the computing system is operating within acceptable operating parameters. The status may direct an action by the peripheral device.

Abstract: Provided are systems and methods for location-aware security configuration of peripheral devices. In various implementations, a location-aware peripheral device comprises an interface and a configuration engine. The interface may communicatively couple the peripheral device to a computing system. The configuration engine may be configured to, upon powering on in the computing system, detect a characteristic of the computing system. In some implementations, the configuration engine may further select a trust level for the computing system. In some implementations, selecting a trust level may include using the detected characteristic to identify a profile stored on the peripheral device. The profile may describe a pre-determined computing system. The configuration engine may further be configured to program the peripheral device with a configuration that is associated with the selected trust level. The configuration may program a feature of the peripheral device.

Abstract: Provided are systems and methods for a location-aware, self-configuring peripheral device. In some implementations, the peripheral device may include two or more personalities. In these implementations, a personality enables the peripheral device to provide a service. In some implementations, the peripheral device may be configured to receive a configuration cycle. In some implementations, the peripheral device may further select a personality from among two or more personalities. The peripheral device may use information derived from the configuration cycle to make this selection. Selecting a personality may further include configuring the peripheral device according to the selected personality.

Abstract: Apparatus and methods are disclosed herein for reducing I/O latency when accessing data using a direct memory access (DMA) engine with a parser. A DMA descriptor indicating memory buffer location can be stored in cache. A DMA descriptor read command is generated and can include a prefetch command. A descriptor with the indicator can be communicated to the DMA engine in response to the read. A second parser can detect the descriptor communication, parse the descriptor, and can prefetch data from memory to cache while the descriptor is being communicated to the DMA engine and/or parsed by the DMA engine parser. When the DMA engine parses the descriptor, data can be accessed from cache rather than memory, to decrease latency.

Abstract: An emulated input/output memory management unit (IOMMU) includes a management processor to perform page table translation in software. The emulated IOMMU can also include a hardware input/output translation lookaside buffer (IOTLB) to store translations between virtual addresses and physical memory addresses. When a translation from a virtual address to a physical address is not found in the IOTLB for an I/O request, the translation can be generated by the management processor using page tables from a memory and can be stored in the IOTLB. Some embodiments can be used to emulate interrupt translation service for message based interrupts for an interrupt controller.

Abstract: Provided are systems and methods for distributing ordering tasks in a computing system that includes master and target devices. In some implementations, a computing device is provided. The computing device may include a master device that is operable to initiate transactions. The computing device may further include a target device that is operable to receive transactions. In some implementations, the master device may be configured to transmit one or more transactions to the target device. The master device may further asynchronously indicate to the target device a number of transactions to execute. The master device may further asynchronously receive from the target device a number of transactions executed. The master device may then signal that at least one transaction from the one or more transactions it sent has completed.

Abstract: Provided are systems and methods for generating transactions with a configurable port. In some implementations, a peripheral device is provided. The peripheral device comprises a configurable port. In some implementations, the configurable port may be configured to receive a first transaction. In these implementations, the first transactions may include an address. The address may include a transaction attribute. In some implementations, the configurable port may extract the transaction attribute and a transaction address from the address. The configurable port may further generate a second transaction that includes the transaction attribute and the transaction address. The configurable port may also transmit the second transaction.

Abstract: A method of transferring data between a host and a PCI device is disclosed. The method comprises mapping a fixed memory-mapping control block in a host memory of the host to a control register of a memory-mapping unit of the PCI device; mapping a dynamic data-access memory block in the host memory to a default memory block in a memory of the PCI device, wherein the memory-mapping unit translates an address between the dynamic data-access memory block and a memory block in the memory of the PCI device; and dynamically modifying a value in the control register of the memory-mapping unit through the fixed memory-mapping control block such that an address of the dynamic data-access memory block in the host memory is translated to a different address in the memory of the PCI device based on the modified value in the control register of the memory-mapping unit.

Abstract: A method for writing data, the method may include: receiving or generating, by an interfacing module, a data unit coherent write request for performing a coherent write operation of a data unit to a first address; receiving, by the interfacing module and from a circuit that comprises a cache and a cache controller, a cache coherency indicator that indicates that a most updated version of the content stored at the first address is stored in the cache; and instructing, by the interfacing module, the cache controller to invalidate a cache line of the cache that stored the most updated version of the first address without sending the most updated version of the content stored at the first address from the cache to a memory module that differs from the cache if a length of the data unit equals a length of the cache line.

Abstract: Techniques for emulating a configuration space by a peripheral device may include receiving a configuration access request, determining that the configuration access request is for a configuration space other than a native configuration space of the peripheral device, and retrieving an emulated configuration from an emulated configuration space. The configuration access request can then be serviced by using the emulated configuration.

Abstract: A method for writing data, the method may include: receiving or generating, by an interfacing module, a data unit coherent write request for performing a coherent write operation of a data unit to a first address; receiving, by the interfacing module and from a circuit that comprises a cache and a cache controller, a cache coherency indicator that indicates that a most updated version of the content stored at the first address is stored in the cache; and instructing, by the interfacing module, the cache controller to invalidate a cache line of the cache that stored the most updated version of the first address without sending the most updated version of the content stored at the first address from the cache to a memory module that differs from the cache if a length of the data unit equals a length of the cache line.

Abstract: A method for writing data, the method may include: receiving or generating, by an interfacing module, a data unit coherent write request for performing a coherent write operation of a data unit to a first address; receiving, by the interfacing module and from a circuit that comprises a cache and a cache controller, a cache coherency indicator that indicates that a most updated version of the content stored at the first address is stored in the cache; and instructing, by the interfacing module, the cache controller to invalidate a cache line of the cache that stored the most updated version of the first address without sending the most updated version of the content stored at the first address from the cache to a memory module that differs from the cache if a length of the data unit equals a length of the cache line.

Abstract: An apparatus including a snoop filter decoupled from a cache and an associated method for snoop filtering are disclosed. The snoop filter is decoupled from the cache such that the cache changes states of lines in the cache from a first state that is a clean state, such as an exclusive (E) state, to a second state that is not a clean state, such as a modified (M) state, without the snoop filter's knowledge. The snoop filter buffers addresses of replaced lines that are unknown to be clean until a write-back associated with the replacement lines occurs, or until actual states of the replaced lines are determined by the snoop filter generating a snoop. A multi-level cache system in which a reallocation or replacement policy is biased to favor replacing certain lines such as inclusive lines, non-temporal lines or prefetched lines that have not been accessed, is also disclosed.

Abstract: Some of the embodiments of the present disclosure provide a method comprising receiving a data packet, and storing the received data packet in a memory; generating a descriptor for the data packet, the descriptor including information for fetching at least a portion of the data packet from the memory; and in advance of a processing core requesting the at least a portion of the data packet to execute a processing operation on the at least a portion of the data packet, fetching the at least a portion of the data packet to a cache based at least in part on information in the descriptor. Other embodiments are also described and claimed.

Abstract: Embodiments provide a method comprising receiving, at a cache associated with a central processing unit that is disposed on an integrated circuit, a request to perform a cache operation on the cache; in response to receiving and processing the request, determining that first data cached in a first cache line of the cache is to be written to a memory that is coupled to the integrated circuit; identifying a second cache line in the cache, the second cache line being complimentary to the first cache line; transmitting a single memory instruction from the cache to the memory to write to the memory (i) the first data from the first cache line and (ii) second data from the second cache line; and invalidating the first data in the first cache line, without invalidating the second data in the second cache line.

Abstract: Some of the embodiments of the present disclosure provide a system-on-chip (SOC) that includes a plurality of processing cores; and a counter update module configured to atomically update a counter that is stored in a storage location, based on a counter update command received from a processing core of the plurality of processing cores; generate an ECC for the updated value of the counter; and write the updated value of the counter and the ECC to the storage location. Other embodiments are also described and claimed.

Abstract: Embodiments of the present disclosure provide a system on a chip (SOC) comprising a processing core, and a cache including a cache instruction port, a cache data port, and a port utilization circuitry configured to selectively fetch instructions through the cache instruction port and selectively pre-fetch instructions through the cache data port. Other embodiments are also described and claimed.