Patents by Inventor Ajit Paranjpe

Ajit Paranjpe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200354828
    Abstract: A chemical vapor deposition system for semiconductor wafer production is disclosed. The system includes a process cluster coupled to a first end of a transfer chamber. The process cluster is maintained at a pressure that is lower than atmospheric pressure. The process cluster is also configured to apply epitaxial layers on one or more wafers loaded onto a wafer carrier. The system also includes an automatic factory interface coupled to a second end of the transfer chamber. The automatic factory interface is maintained at atmospheric pressure. The system includes one or more wafer carrier cleaning modules coupled to the automatic factory interface and configured to clean one or more of the wafer carriers without removing the wafer carriers from the chemical vapor deposition system.
    Type: Application
    Filed: May 8, 2020
    Publication date: November 12, 2020
    Inventors: Alexander I. Gurary, Mandar Deshpande, Ajit Paranjpe
  • Patent number: 10167554
    Abstract: Apparatus for treating wafers using a wafer carrier rotated about an axis is provided with a ring which surrounds the wafer carrier during operation. Treatment gasses directed onto a top surface of the carrier flow outwardly away from the axis over the carrier and over the ring, and pass downstream outside of the ring. The outwardly flowing gasses form a boundary over the carrier and ring. The ring helps to maintain a boundary layer of substantially uniform thickness over the carrier, which promotes uniform treatment of the wafers.
    Type: Grant
    Filed: December 21, 2011
    Date of Patent: January 1, 2019
    Assignee: Veeco Instruments Inc.
    Inventors: Bojan Mitrovic, Guanghua Wei, Eric A. Armour, Ajit Paranjpe
  • Publication number: 20180230596
    Abstract: Apparatus for treating wafers using a wafer carrier rotated about an axis is provided with a ring which surrounds the wafer carrier during operation. Treatment gasses directed onto a top surface of the carrier flow outwardly away from the axis over the carrier and over the ring, and pass downstream outside of the ring. The outwardly flowing gasses form a boundary over the carrier and ring. The ring helps to maintain a boundary layer of substantially uniform thickness over the carrier, which promotes uniform treatment of the wafers.
    Type: Application
    Filed: April 6, 2018
    Publication date: August 16, 2018
    Applicant: Veeco Instruments Inc.
    Inventors: Bojan Mitrovic, Guanghua Wei, Eric A. Armour, Ajit Paranjpe
  • Patent number: 9978934
    Abstract: This disclosure provides various methods for improved etching of spin-transfer torque random access memory (STT-RAM) structures. In one example, the method includes (1) ion beam etch of the stack just past the MTJ at near normal incidence, (2) a short clean-up etch at a larger angle in a windowed mode to remove any redeposited material along the sidewall that extends from just below the MTJ to just above the MTJ, (3) deposition of an encapsulant with controlled step coverage to revert to a vertical or slightly re-entrant profile from the tapered profile generated by the etch steps, (4) ion beam etch of the remainder of the stack at near normal incidence while preserving the encapsulation along the sidewall of the MTJ, (5) clean-up etch at a larger angle and windowed mode to remove redeposited materials from the sidewalls, and (6) encapsulation of the etched stack.
    Type: Grant
    Filed: October 30, 2015
    Date of Patent: May 22, 2018
    Assignee: VEECO Instruments Inc.
    Inventors: Ajit Paranjpe, Boris Druz, Katrina Rook, Narasimhan Srinivasan
  • Patent number: 9938621
    Abstract: Methods are provided for treating wafers using a wafer carrier rotated about an axis. The wafer carrier is provided with a ring which surrounds the wafer carrier during operation. Treatment gasses directed onto a top surface of the carrier flow outwardly away from the axis over the carrier and over the ring, and pass downstream outside of the ring. The outwardly flowing gasses form a boundary over the carrier and ring. The ring helps to maintain a boundary layer of substantially uniform thickness over the carrier, which promotes uniform treatment of the wafers.
    Type: Grant
    Filed: May 11, 2016
    Date of Patent: April 10, 2018
    Assignee: Veeco Instruments Inc.
    Inventors: Bojan Mitrovic, Guanghua Wei, Eric A. Armour, Ajit Paranjpe
  • Patent number: 9761671
    Abstract: A spalling process can be employed to generate a fracture at a predetermined depth within a high quality crystalline nitride substrate, such as a bulk GaN substrate. A first crystalline conductive film layer can be separated, along the line of fracture, from the crystalline nitride substrate and subsequently bonded to a layered stack including a traditional lower-cost substrate. If the spalled surface of the first crystalline conductive film layer is exposed in the resulting structure, the structure can act as a substrate on which high quality GaN-based devices can be grown.
    Type: Grant
    Filed: December 30, 2014
    Date of Patent: September 12, 2017
    Assignee: Veeco Instruments, Inc.
    Inventors: Ajit Paranjpe, Craig Metzner, Joe Lamb
  • Publication number: 20170125668
    Abstract: This disclosure provides various methods for improved etching of spin-transfer torque random access memory (STT-RAM) structures. In one example, the method includes (1) ion beam etch of the stack just past the MTJ at near normal incidence, (2) a short clean-up etch at a larger angle in a windowed mode to remove any redeposited material along the sidewall that extends from just below the MTJ to just above the MTJ, (3) deposition of an encapsulant with controlled step coverage to revert to a vertical or slightly re-entrant profile from the tapered profile generated by the etch steps, (4) ion beam etch of the remainder of the stack at near normal incidence while preserving the encapsulation along the sidewall of the MTJ, (5) clean-up etch at a larger angle and windowed mode to remove redeposited materials from the sidewalls, and (6) encapsulation of the etched stack.
    Type: Application
    Filed: October 30, 2015
    Publication date: May 4, 2017
    Inventors: Ajit Paranjpe, Boris Druz, Katrina Rook, Narasimhan Srinivasan
  • Publication number: 20170076972
    Abstract: A wafer carrier for a plurality of wafers, the wafer carrier having a platen with a plurality of openings and a plurality of wafer retention platforms, the platen configured to rotate about a first axis, the plurality of wafer retention platforms configured to rotate about respective second axes, each of the wafer retention platforms rotatably coupled to one of the plurality of openings by friction reducing bearings, the platen and the plurality of wafer retention platforms and the friction reducing bearings all being constructed of the same material.
    Type: Application
    Filed: September 15, 2016
    Publication date: March 16, 2017
    Inventors: Sandeep Krishnan, Lukas Urban, Alexander Gurary, Keng Moy, Ajit Paranjpe
  • Publication number: 20160251758
    Abstract: Apparatus for treating wafers using a wafer carrier rotated about an axis is provided with a ring which surrounds the wafer carrier during operation. Treatment gasses directed onto a top surface of the carrier flow outwardly away from the axis over the carrier and over the ring, and pass downstream outside of the ring. The outwardly flowing gasses form a boundary over the carrier and ring. The ring helps to maintain a boundary layer of substantially uniform thickness over the carrier, which promotes uniform treatment of the wafers.
    Type: Application
    Filed: May 11, 2016
    Publication date: September 1, 2016
    Inventors: Bojan Mitrovic, Guanghua Wei, Eric A. Armour, Ajit Paranjpe
  • Publication number: 20160160387
    Abstract: A linear cluster deposition system includes a plurality of reaction chambers positioned in a linear horizontal arrangement. First and second reactant gas manifolds are coupled to respective process gas input port of each of the reaction chambers. An exhaust gas manifold having a plurality of exhaust gas inputs is coupled to the exhaust gas output port of each of the plurality of reaction chambers. A substrate transport vehicle transports at least one of a substrate and a substrate carrier that supports at least one substrate into and out of substrate transfer ports of each of the reaction chambers. At least one of a flow rate of process gas into the process gas input port of each of the reaction chambers and a pressure in each of the reaction chambers being chosen so that process conditions are substantially the same in at least two of the reaction chambers.
    Type: Application
    Filed: January 15, 2016
    Publication date: June 9, 2016
    Applicant: Veeco Instruments Inc
    Inventors: William E. Quinn, Alexander Gurary, Ajit Paranjpe, Maria D. Ferreira, Roger P. Fremgen, Eric A. Armour
  • Patent number: 9356188
    Abstract: A stressor layer is applied to a semiconducting stack in order to separate the semiconducting stack at a predetermined depth. Tensile force is applied to the stressor layer, fracturing the semiconducting stack at the predetermined depth and allowing the resulting upper portion of the semiconducting stack to be used in manufacturing a semiconducting end-product (e.g., a light-emitting diode). The resulting lower portion of the semiconducting stack may be reused to grow a new semiconducting stack thereon.
    Type: Grant
    Filed: September 8, 2014
    Date of Patent: May 31, 2016
    Assignee: Veeco Instruments, Inc.
    Inventors: Ajit Paranjpe, Jia Lee, Craig Metzner
  • Publication number: 20160118291
    Abstract: Wafer carriers and methods for moving wafers in a reactor. The wafer carrier may include a platen with a plurality of compartments and a plurality of wafer platforms. The platen is configured to rotate about a first axis. Each of the wafer platforms is associated with one of the compartments and is configured to rotate about a respective second axis relative to the respective compartment. The platen and the wafer platforms rotate with different angular velocities to create planetary motion therebetween. The method may include rotating a platen about a first axis of rotation. The method further includes rotating each of a plurality of wafer platforms carried on the platen and carrying the wafers about a respective second axis of rotation and with a different angular velocity than the platen to create planetary motion therebetween.
    Type: Application
    Filed: January 4, 2016
    Publication date: April 28, 2016
    Inventors: Adrian Celaru, Todd Arthur Luse, Ajit Paranjpe, Joseph Scandariato, Qingfu Tang
  • Publication number: 20150187888
    Abstract: A spalling process can be employed to generate a fracture at a predetermined depth within a high quality crystalline nitride substrate, such as a bulk GaN substrate. A first crystalline conductive film layer can be separated, along the line of fracture, from the crystalline nitride substrate and subsequently bonded to a layered stack including a traditional lower-cost substrate. If the spalled surface of the first crystalline conductive film layer is exposed in the resulting structure, the structure can act as a substrate on which high quality GaN-based devices can be grown.
    Type: Application
    Filed: December 30, 2014
    Publication date: July 2, 2015
    Inventors: Ajit Paranjpe, Craig Metzner, Joe Lamb
  • Publication number: 20150069420
    Abstract: A stressor layer is applied to a semiconducting stack in order to separate the semiconducting stack at a predetermined depth. Tensile force is applied to the stressor layer, fracturing the semiconducting stack at the predetermined depth and allowing the resulting upper portion of the semiconducting stack to be used in manufacturing a semiconducting end-product (e.g., a light-emitting diode). The resulting lower portion of the semiconducting stack may be reused to grow a new semiconducting stack thereon.
    Type: Application
    Filed: September 8, 2014
    Publication date: March 12, 2015
    Inventors: Ajit Paranjpe, Jia Lee, Craig Metzner
  • Publication number: 20140326186
    Abstract: A VPE reactor is improved by providing temperature control to within 0.5° C., and greater process gas uniformity via novel reactor shaping, unique wafer motion structures, improvements in thermal control systems, improvements in gas flow structures, improved methods for application of gas and temperature, and improved control systems for detecting and reducing process variation.
    Type: Application
    Filed: July 16, 2014
    Publication date: November 6, 2014
    Inventors: Ajit Paranjpe, Alexander Gurary, William Quinn
  • Patent number: 8562746
    Abstract: A structure for a chemical vapor deposition reactor includes a support element defining oppositely-facing substantially planar upper and lower surfaces and a vertical rotational axis substantially perpendicular to the upper and lower surfaces, and a plurality of carrier sections releasably engaged with the support element. Each carrier section can include oppositely-facing substantially planar top and bottom surfaces and at least one aperture extending between the top and bottom surfaces. The carrier sections can be disposed on the support element with the bottom surfaces of the carrier sections facing toward the upper surface of the support element, so that wafers can be held in the apertures of the carrier sections with one surface of each wafer confronting the support element and an opposite surface exposed at the top surface of the carrier sections.
    Type: Grant
    Filed: December 15, 2010
    Date of Patent: October 22, 2013
    Assignee: Veeco Instruments Inc.
    Inventors: Alexander I. Gurary, Joseph Arthur Kraus, Ajit Paranjpe, William E. Quinn, David Albert Crewe
  • Publication number: 20130065403
    Abstract: A wafer carrier used in wafer treatments such as chemical vapor deposition has pockets for holding the wafers and support surfaces for supporting the wafers above the floors of the pockets. The carrier is provided with thermal control features such as trenches which form thermal barriers having lower thermal conductivity than surrounding portions of the carrier. These thermal control features promote a more uniform temperature distribution across the wafer surfaces and across the carrier top surface.
    Type: Application
    Filed: November 9, 2012
    Publication date: March 14, 2013
    Inventors: Ajit Paranjpe, Boris Volf, Eric A. Armour, Sandeep Krishnan, Guanghua Wei, Lukas Urban
  • Publication number: 20120272892
    Abstract: A VPE reactor is improved by providing temperature control to within 0.5° C., and greater process gas uniformity via novel reactor shaping, unique wafer motion structures, improvements in thermal control systems, improvements in gas flow structures, improved methods for application of gas and temperature, and improved control systems for detecting and reducing process variation.
    Type: Application
    Filed: April 6, 2012
    Publication date: November 1, 2012
    Applicant: Veeco Instruments Inc.
    Inventors: Ajit Paranjpe, Alexander Gurary, William Quinn
  • Publication number: 20120223048
    Abstract: An inline processing system for patterning magnetic recording layers on hard discs for use in a hard disc drive. Discs are processed on both sides simultaneously in a vertical orientation, in round plate-like holders called MDCs. A plurality (as many as 10) discs are held in a dial carrier of the MDC, and transferred from one process station to another. The dial carrier of the MDC may be rotated and/or angled at up to 70° from normal in each process station, so that one or a plurality of process sources may treat the discs simultaneously. This configuration provides time savings and a reduction in the number and size of process sources needed. A mask enhancement process for patterning of magnetic media, and a filling and planarizing process used therewith, are also disclosed.
    Type: Application
    Filed: August 26, 2010
    Publication date: September 6, 2012
    Applicant: VEECO PROCESS EQUIPMENT INC.
    Inventors: Ajit Paranjpe, Todd A. Luse, Roger P. Fremgen, Narasimhan Srinivasan, Boris L. Druz, Katrina Rook, Adrian Celaru
  • Publication number: 20120216712
    Abstract: Composition and method for depositing ruthenium. A composition containing ruthenium tetroxide RuO4 is used as a precursor solution 608 to coat substrates 400 via ALD, plasma enhanced deposition, and/or CVD. Periodic plasma densification may be used.
    Type: Application
    Filed: January 19, 2010
    Publication date: August 30, 2012
    Inventors: Ajit Paranjpe, Vinayak V. Vats, Randhir Bubber