Patents by Inventor Ajit Paranjpe
Ajit Paranjpe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20120171870Abstract: Apparatus for treating wafers using a wafer carrier rotated about an axis is provided with a ring which surrounds the wafer carrier during operation. Treatment gasses directed onto a top surface of the carrier flow outwardly away from the axis over the carrier and over the ring, and pass downstream outside of the ring. The outwardly flowing gasses form a boundary over the carrier and ring. The ring helps to maintain a boundary layer of substantially uniform thickness over the carrier, which promotes uniform treatment of the wafers.Type: ApplicationFiled: December 21, 2011Publication date: July 5, 2012Applicant: VEECO INSTRUMENTS INC.Inventors: Bojan Mitrovic, Guanghua Wei, Eric A. Armour, Ajit Paranjpe
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Publication number: 20120156374Abstract: A structure for a chemical vapor deposition reactor includes a support element defining oppositely-facing substantially planar upper and lower surfaces and a vertical rotational axis substantially perpendicular to the upper and lower surfaces, and a plurality of carrier sections releasably engaged with the support element. Each carrier section can include oppositely-facing substantially planar top and bottom surfaces and at least one aperture extending between the top and bottom surfaces. The carrier sections can be disposed on the support element with the bottom surfaces of the carrier sections facing toward the upper surface of the support element, so that wafers can be held in the apertures of the carrier sections with one surface of each wafer confronting the support element and an opposite surface exposed at the top surface of the carrier sections.Type: ApplicationFiled: December 15, 2010Publication date: June 21, 2012Applicant: Veeco Instruments Inc.Inventors: Alexander I. Gurary, Joseph Arthur Kraus, Ajit Paranjpe, William E. Quinn, David Albert Crewe
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Publication number: 20120058630Abstract: A linear cluster deposition system includes a plurality of reaction chambers positioned in a linear horizontal arrangement. First and second reactant gas manifolds are coupled to respective process gas input port of each of the reaction chambers. An exhaust gas manifold having a plurality of exhaust gas inputs is coupled to the exhaust gas output port of each of the plurality of reaction chambers. A substrate transport vehicle transports at least one of a substrate and a substrate carrier that supports at least one substrate into and out of substrate transfer ports of each of the reaction chambers. At least one of a flow rate of process gas into the process gas input port of each of the reaction chambers and a pressure in each of the reaction chambers being chosen so that process conditions are substantially the same in at least two of the reaction chambers.Type: ApplicationFiled: September 8, 2010Publication date: March 8, 2012Applicant: Veeco Instruments Inc.Inventors: William E. Quinn, Alexander Gurary, Ajit Paranjpe, Maria D. Ferreira, Roger P. Fremgen, JR., Eric A. Armour
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Publication number: 20110290175Abstract: A multi-chamber CVD system includes a plurality of substrate carriers where each substrate carrier is adapted to support at least one substrate. A plurality of enclosures are each configured to form a deposition chamber enclosing one of the plurality of substrate carriers to maintain an independent chemical vapor deposition process chemistry for performing a processing step. A transport mechanism transports each of the plurality of substrate carriers to each of the plurality of enclosures in discrete steps that allow processing steps to be performed in the plurality of enclosures for a predetermined time. In some embodiments, the substrate carrier can be rotatable.Type: ApplicationFiled: July 18, 2011Publication date: December 1, 2011Applicant: VEECO INSTRUMENTS, INC.Inventors: Ajit Paranjpe, Eric A. Armour, William E. Quinn
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Patent number: 7713881Abstract: A method for void free filling with in-situ doped amorphous silicon of a deep trench structure is provided in which a first fill is carried out in a way so that film deposition occurs from the bottom of the trench upwards, with step coverage well in excess of 100%. In a second fill step, deposition conditions are changed to reduce the impact of dopant on deposition rate, and deposition proceeds at a rate which exceeds the deposition rate of the first fill. In an application of this method to the formation of deep trench capacitor structures, the intermediate steps further including the capping of the void free filled trench with a thick layer of amorphous silicon, planarization of the wafer thereafter, followed by a thermal anneal to re-distribute the dopant within the filled trench. Thereafter, additional steps can be performed to complete the formation of the capacitor structure.Type: GrantFiled: August 27, 2008Date of Patent: May 11, 2010Assignee: Applied Materials, Inc.Inventors: Ajit Paranjpe, Somnath Nag
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Publication number: 20080318441Abstract: A method for void free filling with in-situ doped amorphous silicon of a deep trench structure is provided in which a first fill is carried out in a way so that film deposition occurs from the bottom of the trench upwards, with step coverage well in excess of 100%. In a second fill step, deposition conditions are changed to reduce the impact of dopant on deposition rate, and deposition proceeds at a rate which exceeds the deposition rate of the first fill. In an application of this method to the formation of deep trench capacitor structures, the intermediate steps further including the capping of the void free filled trench with a thick layer of amorphous silicon, planarization of the wafer thereafter, followed by a thermal anneal to re-distribute the dopant within the filled trench. Thereafter, additional steps can be performed to complete the formation of the capacitor structure.Type: ApplicationFiled: August 27, 2008Publication date: December 25, 2008Applicant: APPLIED MATERIALS, INC.Inventors: Ajit Paranjpe, Somnath Nag
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Patent number: 7446366Abstract: A method for void free filling with in-situ doped amorphous silicon of a deep trench structure is provided in which a first fill is carried out in at a temperature, pressure and dopant to silane ratio such that film deposition occurs from the bottom of the trench upwards. By way of this first fill, step coverages well in excess 100% are achieved. In the second fill step, deposition is carried out under changed conditions so as to reduce the impact of dopant on deposition rate, whereby trench fill is completed at a deposition rate which exceeds the deposition rate of the first fill. In an application of this method to the formation of deep trench capacitor structures, the intermediate steps further including the capping of the void free filled trench with a thick layer of amorphous silicon, planarization of the wafer thereafter, followed by a thermal anneal to re-distribute the dopant within the filled trench. Thereafter, additional steps can be performed to complete the formation of the capacitor structure.Type: GrantFiled: May 30, 2006Date of Patent: November 4, 2008Assignee: Applied Materials, Inc.Inventors: Ajit Paranjpe, Somnath Nag
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Patent number: 7354848Abstract: A CMOS gate stack that increases the inversion capacitance compared to a conventional CMOS gate stack has been described. Using a poly-SiGe gate, instead of the conventional poly-Si gate near the gate dielectric layer, increases the amount of implanted dopant that can be activated. This increase overcomes the polysilicon depletion problem that limits the inversion capacitance in the conventional CMOS gate stack. To integrate the poly-SiGe layer into the gate stack, a thin ?-Si layer is deposited between the gate dielectric layer and the poly-SiGe layer. To ensure proper salicide formation, a poly-Si layer is capped over the poly-SiGe layer. In order to obtain a fined-grained poly-Si over poly-SiGe, a second ?-Si layer is deposited between the poly-Si layer and the poly-SiGe layer.Type: GrantFiled: May 30, 2006Date of Patent: April 8, 2008Assignee: Applied Materials, Inc.Inventors: Ajit Paranjpe, Kangzhan Zhang
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Publication number: 20060231925Abstract: A CMOS gate stack that increases the inversion capacitance compared to a conventional CMOS gate stack has been described. Using a poly-SiGe gate, instead of the conventional poly-Si gate near the gate dielectric layer, increases the amount of implanted dopant that can be activated. This increase overcomes the polysilicon depletion problem that limits the inversion capacitance in the conventional CMOS gate stack. To integrate the poly-SiGe layer into the gate stack, a thin ?-Si layer is deposited between the gate dielectric layer and the poly-SiGe layer. To ensure proper salicide formation, a poly-Si layer is capped over the poly-SiGe layer. In order to obtain a fined-grained poly-Si over poly-SiGe, a second ?-Si layer is deposited between the poly-Si layer and the poly-SiGe layer.Type: ApplicationFiled: May 30, 2006Publication date: October 19, 2006Inventors: Ajit Paranjpe, Kangzhan Zhang
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Publication number: 20060234470Abstract: A method for void free filling with in-situ doped amorphous silicon of a deep trench structure is provided in which a first fill is carried out in at a temperature, pressure and dopant to silane ratio such that film deposition occurs from the bottom of the trench upwards. By way of this first fill, step coverages well in excess 100% are achieved. In the second fill step, deposition is carried out under changed conditions so as to reduce the impact of dopant on deposition rate, whereby trench fill is completed at a deposition rate which exceeds the deposition rate of the first fill. In an application of this method to the formation of deep trench capacitor structures, the intermediate steps further including the capping of the void free filled trench with a thick layer of amorphous silicon, planarization of the wafer thereafter, followed by a thermal anneal to re-distribute the dopant within the filled trench. Thereafter, additional steps can be performed to complete the formation of the capacitor structure.Type: ApplicationFiled: May 30, 2006Publication date: October 19, 2006Inventors: Ajit Paranjpe, Somnath Nag
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Patent number: 7109097Abstract: A method for void free filling with in-situ doped amorphous silicon of a deep trench structure is provided in which a first fill is carried out in at a temperature, pressure and dopant to silane ratio such that film deposition occurs from the bottom of the trench upwards. By way of this first fill, step coverages well in excess 100% are achieved. In the second fill step, deposition is carried out under changed conditions so as to reduce the impact of dopant on deposition rate, whereby trench fill is completed at a deposition rate which exceeds the deposition rate of the first fill. In an application of this method to the formation of deep trench capacitor structures, the intermediate steps further including the capping of the void free filled trench with a thick layer of amorphous silicon, planarization of the wafer thereafter, followed by a thermal anneal to re-distribute the dopant within the filled trench. Thereafter, additional steps can be performed to complete the formation of the capacitor structure.Type: GrantFiled: December 14, 2004Date of Patent: September 19, 2006Assignee: Applied Materials, Inc.Inventors: Ajit Paranjpe, Somnath Nag
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Publication number: 20060128139Abstract: A method for void free filling with in-situ doped amorphous silicon of a deep trench structure is provided in which a first fill is carried out in at a temperature, pressure and dopant to silane ratio such that film deposition occurs from the bottom of the trench upwards. By way of this first fill, step coverages well in excess 100% are achieved. In the second fill step, deposition is carried out under changed conditions so as to reduce the impact of dopant on deposition rate, whereby trench fill is completed at a deposition rate which exceeds the deposition rate of the first fill. In an application of this method to the formation of deep trench capacitor structures, the intermediate steps further including the capping of the void free filled trench with a thick layer of amorphous silicon, planarization of the wafer thereafter, followed by a thermal anneal to re-distribute the dopant within the filled trench. Thereafter, additional steps can be performed to complete the formation of the capacitor structure.Type: ApplicationFiled: December 14, 2004Publication date: June 15, 2006Inventors: Ajit Paranjpe, Somnath Nag
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Publication number: 20060084283Abstract: A silicon nitride layer is deposited on a substrate within a processing region by introducing a silicon containing precursor into the processing region, exhausting gases in the processing region including the silicon containing precursor while uniformly, gradually reducing a pressure of the processing region, introducing a nitrogen containing precursor into the processing region, and exhausting gases in the processing region including the nitrogen containing precursor while uniformly, gradually reducing a pressure of the processing region. During the steps of exhausting, the slope of the pressure decrease with respect to time is substantially constant.Type: ApplicationFiled: October 20, 2004Publication date: April 20, 2006Inventors: Ajit Paranjpe, Kangzhan Zhang, Brendan McDougall, Wayne Vereb, Michael Patten, Alan Goldman, Somnath Nag
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Publication number: 20060060920Abstract: A CMOS gate stack that increases the inversion capacitance compared to a conventional CMOS gate stack has been described. Using a poly-SiGe gate, instead of the conventional poly-Si gate near the gate dielectric layer, increases the amount of implanted dopant that can be activated. This increase overcomes the polysilicon depletion problem that limits the inversion capacitance in the conventional CMOS gate stack. To integrate the poly-SiGe layer into the gate stack, a thin ?-Si layer is deposited between the gate dielectric layer and the poly-SiGe layer. To ensure proper salicide formation, a poly-Si layer is capped over the poly-SiGe layer. In order to obtain a fined-grained poly-Si over poly-SiGe, a second ?-Si layer is deposited between the poly-Si layer and the poly-SiGe layer.Type: ApplicationFiled: September 17, 2004Publication date: March 23, 2006Inventors: Ajit Paranjpe, Kangzhan Zhang
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Publication number: 20050188923Abstract: A substrate carrier for a parallel wafer processing reactor supports a plurality of substrates. The substrate carrier includes a plurality of susceptors, which may be thermal plates or annular rings that are arranged horizontally in a vertical stack. The substrates are mounted between pairs of susceptors on two or more supports provided around the outer periphery of the susceptors. The number of substrates mounted between each pair of susceptors may the same or different but is two or more between at least one pair of susceptors.Type: ApplicationFiled: October 15, 2004Publication date: September 1, 2005Inventors: Robert Cook, Ronald Stevens, Peter Schwartz, Cesar Tejamo, Vebjorn Nilsen, Gabriel Ormonde, Ajit Paranjpe, Somnath Nag, Michael Patten
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Patent number: 6592728Abstract: A dual collimation deposition apparatus and method are disclosed in which the dual collimation apparatus includes at least a long-throw collimator in combination with one or more physical collimators. A new physical collimator and shield design are also disclosed for improved process uniformity and increased equipment productivity.Type: GrantFiled: August 4, 1998Date of Patent: July 15, 2003Assignee: Veeco-CVC, Inc.Inventors: Ajit Paranjpe, Peter Schwartz, Jacques Kools, Kang Song, Dorian Heimanson, Mehrdad Moslehi
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Patent number: 6572744Abstract: A dual collimation deposition apparatus and method are disclosed in which the dual collimation apparatus includes at least a long-throw collimator in combination with one or more physical collimators. A new physical collimator and shield design are also disclosed for improved process uniformity and increased equipment productivity.Type: GrantFiled: January 22, 2001Date of Patent: June 3, 2003Assignee: Veeco Instruments, Inc.Inventors: Ajit Paranjpe, Peter Schwartz, Jacques Kools, Kang Song, Dorian Heimanson, Mehrdad Moslehi