Abstract: Apparatus for semiconductor device structures and related fabrication methods are provided. A method for fabricating a semiconductor device structure on an isolated region of semiconductor material comprises forming a plurality of gate structures overlying the isolated region of semiconductor material and masking edge portions of the isolated region of semiconductor material. While the edge portions are masked, the fabrication method continues by forming recesses between gate structures of the plurality of gate structures and forming stressor regions in the recesses. The method continues by unmasking the edge portions and implanting ions of a conductivity-determining impurity type into the stressor regions and the edge portions.

Abstract: A semiconductor device is formed with low resistivity self aligned silicide contacts with high-K/metal gates. Embodiments include postponing silicidation of a metal layer on source/drain regions in a silicon substrate until deposition of a high-K dielectric, thereby preserving the physical and morphological properties of the silicide film and improving device performance. An embodiment includes forming a replaceable gate electrode on a silicon-containing substrate, forming source/drain regions, forming a metal layer on the source/drain regions, forming an ILD over the metal layer on the substrate, removing the replaceable gate electrode, thereby forming a cavity, depositing a high-K dielectric layer in the cavity at a temperature sufficient to initiate a silicidation reaction between the metal layer and underlying silicon, and forming a metal gate electrode on the high-K dielectric layer.

Abstract: A first bias charge is provided to first bias region at a first level of an electronic device, the first bias region directly underlying a first transistor having a channel region at a second level that is electrically isolated from the first bias region. A voltage threshold of the first transistor is based upon the first bias charge. A second bias charge is provided to second bias region at the first level of an electronic device, the second bias region directly underlying a second transistor having a channel region at a second level that is electrically isolated from the first bias region. A voltage threshold of the second transistor is based upon the second bias charge.

Abstract: A method of fabricating p-type metal oxide semiconductor (PMOS) transistor devices on a common substrate is presented. The method provides a first portion of semiconductor material and a second portion of semiconductor material on the common substrate. The first portion of semiconductor material and the second portion of semiconductor material are insulated from each other. The method continues by creating first PMOS transistor devices using the first portion of semiconductor material. The first PMOS transistor devices include stressor regions that impart compressive stress to channel regions of the first PMOS transistor devices. The method also creates second PMOS transistor devices using the second portion of semiconductor material. The second PMOS transistor devices do not include channel stressor regions.

Abstract: Apparatus for semiconductor device structures and related fabrication methods are provided. A method for fabricating a semiconductor device structure on an isolated region of semiconductor material comprises forming a plurality of gate structures overlying the isolated region of semiconductor material and masking edge portions of the isolated region of semiconductor material. While the edge portions are masked, the fabrication method continues by forming recesses between gate structures of the plurality of gate structures and forming stressor regions in the recesses. The method continues by unmasking the edge portions and implanting ions of a conductivity-determining impurity type into the stressor regions and the edge portions.

Abstract: A semiconductor device is formed with low resistivity self aligned silicide contacts with high-K/metal gates. Embodiments include postponing silicidation of a metal layer on source/drain regions in a silicon substrate until deposition of a high-K dielectric, thereby preserving the physical and morphological properties of the silicide film and improving device performance. An embodiment includes forming a replaceable gate electrode on a silicon-containing substrate, forming source/drain regions, forming a metal layer on the source/drain regions, forming an ILD over the metal layer on the substrate, removing the replaceable gate electrode, thereby forming a cavity, depositing a high-K dielectric layer in the cavity at a temperature sufficient to initiate a silicidation reaction between the metal layer and underlying silicon, and forming a metal gate electrode on the high-K dielectric layer.

Abstract: The present invention is directed to a transistor with an asymmetric silicon germanium source region, and various methods of making same. In one illustrative embodiment, the transistor includes a gate electrode formed above a semiconducting substrate comprised of silicon, a doped source region comprising a region of epitaxially grown silicon that is doped with germanium formed in the semiconducting substrate and a doped drain region formed in the semiconducting substrate.

Abstract: A semiconductor device is formed with low resistivity self aligned silicide contacts with high-K/metal gates. Embodiments include postponing silicidation of a metal layer on source/drain regions in a silicon substrate until deposition of a high-K dielectric, thereby preserving the physical and morphological properties of the silicide film and improving device performance. An embodiment includes forming a replaceable gate electrode on a silicon-containing substrate, forming source/drain regions, forming a metal layer on the source/drain regions, forming an ILD over the metal layer on the substrate, removing the replaceable gate electrode, thereby forming a cavity, depositing a high-K dielectric layer in the cavity at a temperature sufficient to initiate a silicidation reaction between the metal layer and underlying silicon, and forming a metal gate electrode on the high-K dielectric layer.

Abstract: A semiconductor device is formed with low resistivity self aligned silicide contacts with high-K/metal gates. Embodiments include postponing silicidation of a metal layer on source/drain regions in a silicon substrate until deposition of a high-K dielectric, thereby preserving the physical and morphological properties of the silicide film and improving device performance. An embodiment includes forming a replaceable gate electrode on a silicon-containing substrate, forming source/drain regions, forming a metal layer on the source/drain regions, forming an ILD over the metal layer on the substrate, removing the replaceable gate electrode, thereby forming a cavity, depositing a high-K dielectric layer in the cavity at a temperature sufficient to initiate a silicidation reaction between the metal layer and underlying silicon, and forming a metal gate electrode on the high-K dielectric layer.

Abstract: The present invention is directed to a transistor with an asymmetric silicon germanium source region, and various methods of making same. In one illustrative embodiment, the transistor includes a gate electrode formed above a semiconducting substrate comprised of silicon, a doped source region comprising a region of epitaxially grown silicon that is doped with germanium formed in the semiconducting substrate and a doped drain region formed in the semiconducting substrate.

Abstract: Apparatus for semiconductor device structures and related fabrication methods are provided. A method for fabricating a semiconductor device structure on an isolated region of semiconductor material comprises forming a plurality of gate structures overlying the isolated region of semiconductor material and masking edge portions of the isolated region of semiconductor material. While the edge portions are masked, the fabrication method continues by forming recesses between gate structures of the plurality of gate structures and forming stressor regions in the recesses. The method continues by unmasking the edge portions and implanting ions of a conductivity-determining impurity type into the stressor regions and the edge portions.

Abstract: A semiconductor device is provided which includes a substrate including an inactive region and an active region, a gate electrode structure having portions overlying the active region, a compressive layer overlying the active region, and a tensile layer overlying the inactive region and located outside the active region. The active region has a lateral edge which defines a width of the active region, and a transverse edge which defines a length of the active region. The gate electrode structure includes: a common portion spaced apart from the active region; a plurality of gate electrode finger portions integral with the common portion, and a plurality of fillet portions integral with the common portion and the gate electrode finger portions. A portion of each gate electrode finger portion overlies the active region. The fillet portions are disposed between the common portion and the gate electrode finger portions, and do not overlie the active region.

Abstract: The present invention is directed to a transistor with an asymmetric silicon germanium source region, and various methods of making same. In one illustrative embodiment, the transistor includes a gate electrode formed above a semiconducting substrate comprised of silicon, a doped source region comprising a region of epitaxially grown silicon that is doped with germanium formed in the semiconducting substrate and a doped drain region formed in the semiconducting substrate.

Abstract: A method of fabricating p-type metal oxide semiconductor (PMOS) transistor devices on a common substrate is presented. The method provides a first portion of semiconductor material and a second portion of semiconductor material on the common substrate. The first portion of semiconductor material and the second portion of semiconductor material are insulated from each other. The method continues by creating first PMOS transistor devices using the first portion of semiconductor material. The first PMOS transistor devices include stressor regions that impart compressive stress to channel regions of the first PMOS transistor devices. The method also creates second PMOS transistor devices using the second portion of semiconductor material. The second PMOS transistor devices do not include channel stressor regions.

Abstract: A method includes receiving design data associated with an integrated circuit device. The integrated circuit device includes a first element having a corner defined therein and a second element overlapping the first element. A dimension specified for the first element in the design data is adjusted based on a distance between the second element and the corner. The integrated circuit device is simulated based on the adjusted dimension.

Abstract: The techniques and technologies described herein relate to the automatic creation of photoresist masks for stress liners used with semiconductor based transistor devices. The stress liner masks are generated with automated design tools that leverage layout data corresponding to features, devices, and structures on the wafer. A resulting stress liner mask (and wafers fabricated using the stress liner mask) defines a stress liner coverage area that extends beyond the boundary of the transistor area and into a stress insensitive area of the wafer. The extended stress liner further enhances performance of the respective transistor by providing additional compressive/tensile stress.

Abstract: A semiconductor device is provided which includes a substrate including an inactive region and an active region, a gate electrode structure having portions overlying the active region, a compressive layer overlying the active region, and a tensile layer overlying the inactive region and located outside the active region. The active region has a lateral edge which defines a width of the active region, and a transverse edge which defines a length of the active region. The gate electrode structure includes: a common portion spaced apart from the active region; a plurality of gate electrode finger portions integral with the common portion, and a plurality of fillet portions integral with the common portion and the gate electrode finger portions. A portion of each gate electrode finger portion overlies the active region. The fillet portions are disposed between the common portion and the gate electrode finger portions, and do not overlie the active region.

Abstract: A stress-enhanced semiconductor device is provided which includes a substrate having an inactive region and an active region, a first-type stress layer overlying at least a portion of the active region, and a second-type stress layer. The active region includes a first lateral edge which defines a first width of the active region, and a second lateral edge which defines a second width of the active region. The second-type stress layer is disposed adjacent the second lateral edge of the active region.

Abstract: A semiconductor device is provided which includes a substrate including an inactive region and an active region, a gate electrode structure having portions overlying the active region, a compressive layer overlying the active region, and a tensile layer overlying the inactive region and located outside the active region. The active region has a lateral edge which defines a width of the active region, and a transverse edge which defines a length of the active region. The gate electrode structure includes: a common portion spaced apart from the active region; a plurality of gate electrode finger portions integral with the common portion, and a plurality of fillet portions integral with the common portion and the gate electrode finger portions. A portion of each gate electrode finger portion overlies the active region. The fillet portions are disposed between the common portion and the gate electrode finger portions, and do not overlie the active region.

Abstract: The halo implant technique described herein employs a halo implant mask that creates a halo implant shadowing effect during halo dopant bombardment. A first transistor device structure and a second transistor device structure are formed on a wafer such that they are orthogonally oriented to each other. A common halo implant mask is created with features that prevent halo implantation of the diffusion region of the second transistor device structure during halo implantation of the diffusion region of the first transistor device structure, and with features that prevent halo implantation of the diffusion region of the first transistor device structure during halo implantation of the diffusion region of the second transistor device structure. The orthogonal orientation of the transistor device structures and the pattern of the halo implant mask obviates the need to create multiple implant masks to achieve different threshold voltages for the transistor device structures.