Abstract: Various methods of fabricating a source/drain structure are provided. In one aspect, a method of processing a semiconductor workpiece is provided that includes implanting a neutral ion species into the substrate at a sub-amorphizing dosage to provide a plurality of interstitials and forming a source/drain region in the substrate by implanting impurities of a first conductivity type proximate the plurality of interstitials. The plurality of interstitials retards diffusion of the impurities. Impurity diffusion is retarded, resulting in better activation and a more abrupt impurity profile.

Abstract: Various methods of fabricating a silicide structure are provided. In one aspect, a method of fabricating a circuit structure on a silicon surface is provided that includes exposing the silicon surface to a plasma ambient containing hydrogen and an inert gas, and depositing a metallic material capable of forming silicide on the silicon surface. The metallic material is heated to form a metal silicide on the silicon surface. The method provides for low sheet resistance silicide structures by eliminating native oxide films without the risk of spacer material backsputtering.

Abstract: A method for forming a semiconductor device is provided. A base layer is provided. A first epitaxial layer having a first dopant at a first concentration is formed above the base layer. A second epitaxial layer having a second dopant at a second concentration is formed above the first epitaxial layer. The second concentration is greater than the first concentration. A third epitaxial layer having a third dopant at a third concentration is formed above the second epitaxial layer. The third concentration is less than the second concentration. Ions are implanted in the third epitaxial layer to form an implant region. The implant region is in contact with the second epitaxial layer. A semiconductor device comprises a base layer, first, second, and third epitaxial layers, and an implant region. The first epitaxial layer has a first dopant at a first concentration disposed above the base layer. The second epitaxial layer has a second dopant at a second concentration disposed above the first epitaxial layer.

Abstract: Ultra shallow, low resistance LDD junctions are achieved by forming an LDD implant generating an interstitial-rich section and forming a sub-surface, non-amorphous region generating a vacancy-rich region substantially overlapping the interstitial rich region generated when forming the LDD implant. Embodiments include ion implanting, Ge or Si to form surface amorphous and sub-surface, non-amorphous regions, and implanting B or BF.sub.2 to form the impurity region. Embodiments include forming the sub-surface, non-amorphous region before or after generating the surface amorphous region, and forming the impurity region before or after forming the sub-surface, non-amorphous region but after forming the surface amorphous region.

Abstract: A method of fabricating a transistor is provided. According to the method, a heavy ion is implanted into a silicon substrate so as to amorphize at least a portion of the silicon substrate. The amorphized silicon is substantially free of channels. A dopant is subsequently implanted into the amorphized silicon, and the amorphized silicon substantially contains the implanted dopant. Thereafter, a silicon implanting step is performed to create an excess of vacancies to interstitials within a predetermined range. Enhanced diffusion of the dopant within the predetermined range is mitigated because of the excess of vacancies to interstitials within this predetermined range.

Abstract: A method of making a lightly doped drain transistor includes the steps of forming a gate electrode (52) and a gate oxide (54) over a semiconductor substrate (56) and forming a drain (70) in a drain region (58) and a source (72) in a source region (60) of the substrate (56). The method further includes generating interstitials (62) near a lateral edge of at least one of the drain (70) and the source (72) and thermally treating the substrate (56). The thermal treatment cause the interstitials (62) to enhance a lateral diffusion (84) of the drain (70) under the gate oxide (54) without substantially impacting a vertical diffusion (82) of the drain (70) or the source (72). The enhanced lateral diffusion (84) results in the formation of at least one of a lightly doped drain extension region (75) and a lightly doped source extension region (76) without an increase in a junction depth of the drain (70) or the source (72).

Abstract: A method of reducing an effective channel length of a lightly doped drain transistor (50), includes the steps of forming a gate electrode (52) and a gate oxide (54) over a semiconductor substrate (56) and implanting a drain region (58) of the substrate (56) with a sub-amorphous large tilt angle implant to thereby supply interstitials (62) at a location under the gate oxide (54). The method also includes forming a lightly doped drain extension region (66) in the drain region (58) of the substrate (56) and forming a drain (70) in the drain region (58) and forming a source extension region (67) and a source (72) in a source region (60) of the substrate (56).