Abstract: A semiconductor device includes an active region formed in an upper layer portion of a semiconductor layer of a first conductivity type, and a plurality of electric field relaxation layers disposed from an edge of the active region toward the outside so as to surround the active region. The plurality of electric field relaxation layers include a plurality of first electric field relaxation layers and a plurality of second electric field relaxation layers alternately disposed adjacent to each other, the first electric field relaxation layer and the second electric field relaxation layer adjacent to each other forming a set. Impurities of a second conductivity type are implanted to the first electric field relaxation layers at a first surface density, widths of which becoming smaller as apart from the active region.

Abstract: In the present application, a power semiconductor device includes a first-conductive-type first base region having a first principal surface and a second principal surface opposite to the first principal surface, a second-conductive-type second base region disposed on the first principal surface and at least three groove parts parallel to each other disposed from a surface of the second base region. The device further includes insulating films covering inner walls of the respective groove parts, conductive trench gates filled on the insulating films, a first-conductive-type emitter region disposed in the second base region, and a second-conductive-type collector region disposed on the second principal surface of the first base region. The trench gates embedded in the first groove part and the third groove part are electrically connected to the gate electrode, and the trench gate embedded in the second groove part is electrically connected to the emitter electrode.

Abstract: A source region of a MOSFET includes: a source contact region connected to a source pad; a source extension region adjacent to a channel region in a well region; and a source resistance control region arranged between the source extension region and the source contact region. The source resistance control region is different in an impurity concentration from the source extension region and the source contact region. These three regions are connected in series between the source pad and the channel region in the well region.

Abstract: An electric field buffer layer is formed so as to surround an active region. The electric field buffer layer includes a plurality of P-type impurity layers. Each of the P-type impurity layers includes P-type implantation layers and P-type diffusion layers that are formed so as to respectively surround the P-type implantation layers and contain P-type impurities at a concentration lower than that of the P-type implantation layers. A first P-type implantation layer is formed to be in contact with or to partially overlap the active region. Each of the P-type diffusion layers is formed to have an expansion to a degree to which the first P-type diffusion layer is in contact with or overlaps a second P-type diffusion layer. Intervals between the P-type implantation layers increase from the active region toward the outer peripheral portion of the semiconductor substrate.

Abstract: In a JBS diode using a wide band gap semiconductor, the wide band gap semiconductor has a large built-in voltage, which sometimes causes difficulties for the pn diode portion to turn on, resulting in a problem that resistance to surge currents is not sufficiently ensured. In order to solve this problem, in the wide-band-gap JBS diode, a pn junction of the pn diode is formed away from the Schottky electrode, and well regions are formed so as to have a width narrowed at a portion away from the Schottky electrode.

Abstract: In a high speed switching power semiconductor device having a sense pad, a high voltage is generated during switching operations in well regions under the sense pad due to a displacement current flowing through its flow path with a resistance, whereby the power semiconductor device sometimes breaks down by dielectric breakdown of a thin insulating film such as a gate insulating film. In a power semiconductor device according to the invention, sense-pad well contact holes are provided on well regions positioned under the sense pad and penetrate a field insulating film thicker than the gate insulating film to connect to the source pad, thereby improving reliability.

Abstract: There is provided a trench-gate type semiconductor device that can prevent breakdown of a gate insulating film caused by a displacement current flowing into a protective diffusion layer at a portion of a trench underlying a gate electrode at a turn-off time and simultaneously improves a current density by narrowing a cell pitch. The semiconductor device has a gate electrode 7 embedded into a trench 5 penetrating a base region 3. The gate electrode 7 is disposed into a lattice shape in a planar view, and a protective diffusion layer 13 is formed in a drift layer 2a at the portion underlying thereof. At least one of blocks divided by the gate electrode 7 is a protective contact region 20 on which the trench 5 is entirely formed. A protective contact 21 for connecting the protective diffusion layer 13 at a bottom portion of the trench 5 and a source electrode 9 is disposed on the protective contact region 20.

Abstract: A trench-gate type semiconductor device that can prevent breakdown of a gate insulating film caused by a displacement current flowing into a protective diffusion layer at a portion of a trench underlying a gate electrode at a turn-off time and simultaneously improves a current density by narrowing a cell pitch. The semiconductor device includes a gate electrode embedded into a trench penetrating a base region. The gate electrode is disposed into a lattice shape in a planar view, and a protective diffusion layer is formed in a drift layer at the portion underlying thereof. At least one of blocks divided by the gate electrode is a protective contact region on which the trench is entirely formed. A protective contact for connecting the protective diffusion layer at a bottom portion of the trench and a source electrode is disposed on the protective contact region.

Abstract: A semiconductor device having high breakdown voltage and high reliability without forming an embedded injection layer with high position accuracy. The semiconductor device includes a base as an active area of a second conductivity type formed on a surface layer of a semiconductor layer of a first conductivity type to constitute a semiconductor element; guard rings as a plurality of first impurity regions of the second conductivity type formed on the surface layer of the semiconductor layer spaced apart from each other to respectively surround the base in plan view; and an embedded injection layer as a second impurity region of the second conductivity type embedded in the surface layer of the semiconductor layer to connect at least two bottom portions of the plurality of guard rings.

Abstract: A semiconductor device that can improve reliability while suppressing increase of a conduction loss or a switching loss. In the semiconductor device, when a two-dimensional shape on a main surface of the semiconductor substrate is an unit cell, the shape being a repeating unit of a plurality of well regions periodically disposed in a surface layer of a drift layer, one unit cell and another unit cell adjacent in an x-axis direction are disposed misaligned in a y-axis direction, and one unit cell and another unit cell adjacent in the y-axis direction are disposed misaligned in the x-axis direction.

Abstract: A silicon carbide semiconductor device including an SBD measuring a temperature of a silicon carbide semiconductor element. The silicon carbide semiconductor device includes a MOSFET formed on a silicon carbide epitaxial substrate, and an SBD section measuring a temperature of the MOSFET. The SBD section includes an n-type cathode region in a surface portion of a silicon carbide drift layer; an anode titanium electrode formed on the cathode region, the electrode serving as a Schottky electrode; an n-type cathode contact region of a higher concentration than that of the cathode region, formed in the surface portion of the silicon carbide drift layer to make contact with the cathode region; a cathode ohmic electrode formed on the cathode contact region; and a first p-type well region formed within the silicon carbide drift layer to surround peripheries of the cathode region and the cathode contact region.

Abstract: An electric field buffer layer (13) is formed so as to surround an active region (12) from an outer peripheral portion of the active region (12) toward an outer peripheral portion of a semiconductor substrate (11). The electric field buffer layer (13) includes a plurality of P-type impurity layers (21 to 25). Each of the P-type impurity layers (21 to 25) includes P-type implantation layers (21a to 25a) and P-type diffusion layers (21b to 25b) that are formed so as to respectively surround the P-type implantation layers (21a to 25a) and contain P-type impurities at a concentration lower than that of the P-type implantation layers (21a to 25a). A first P-type implantation layer (21a) is formed to be in contact with or to partially overlap the active region (12). Each of the P-type diffusion layers (21b to 25b) is formed to have an expansion to a degree to which the first P-type diffusion layer (21b) is in contact with or overlaps a second P-type diffusion layer (22b).

Abstract: A semiconductor device capable of suppressing time variation of a threshold voltage and a method of manufacturing the same. A semiconductor device according to the present invention comprises a drift layer formed on a semiconductor substrate, first well regions formed in a surface layer of the drift layer, being apart from one another, a gate insulating film formed, extending on the drift layer and each of the first well regions, a gate electrode selectively formed on the gate insulating film, a source contact hole penetrating through the gate insulating film and reaching the inside of each of the first well regions, and a residual compressive stress layer formed on at least a side surface of the source contact hole, in which a compressive stress remains.

Abstract: A source region of a MOSFET includes: a source contact region connected to a source pad; a source extension region adjacent to a channel region in a well region; and a source resistance control region arranged between the source extension region and the source contact region. The source resistance control region is different in an impurity concentration from the source extension region and the source contact region. These three regions are connected in series between the source pad and the channel region in the well region.

Abstract: A semiconductor device includes a semiconductor substrate of a first conductivity type, a drift layer of the first conductivity type which is formed on a first main surface of the semiconductor substrate, a second well region of a second conductivity type which is formed to surround a cell region of the drift layer, and a source pad for electrically connecting the second well regions and a source region of the cell region through a first well contact hole provided to penetrate a gate insulating film on the second well region, a second well contact hole provided to penetrate a field insulating film on the second well region and a source contact hole.

Abstract: A power semiconductor device includes a second conductive type sense outer-peripheral well formed to surround a plurality of sense wells on the surface of a drift layer, a first conductive type main-cell source region selectively formed on the surface of the main cell well, a first conductive type sense source region selectively formed on the surface of the sense well, a first conductive type capacitor lower electrode region selectively formed on the surface of the sense outer-peripheral well, a gate insulation film formed on the channel regions and on the sense outer-peripheral well, a gate electrode formed on the gate insulation film, and a sense pad electrically connected to the sense well and the sense source region as well as on the sense outer-peripheral well and the capacitor lower electrode region.

Abstract: In a JBS diode using a wide band gap semiconductor, the wide band gap semiconductor has a large built-in voltage, which sometimes causes difficulties for the pn diode portion to turn on, resulting in a problem that resistance to surge currents is not sufficiently ensured. In order to solve this problem, in the wide-band-gap JBS diode, a pn junction of the pn diode is formed away from the Schottky electrode, and well regions are formed so as to have a width narrowed at a portion away from the Schottky electrode.

Abstract: A semiconductor device includes an active region formed in an upper layer portion of a semiconductor layer of a first conductivity type, and a plurality of electric field relaxation layers disposed from an edge of the active region toward the outside so as to surround the active region. The plurality of electric field relaxation layers include a plurality of first electric field relaxation layers and a plurality of second electric field relaxation layers alternately disposed adjacent to each other, the first electric field relaxation layer and the second electric field relaxation layer adjacent to each other forming a set. Impurities of a second conductivity type are implanted to the first electric field relaxation layers at a first surface density, widths of which becoming smaller as apart from the active region.

Abstract: A semiconductor device that can improve reliability while suppressing increase of a conduction loss or a switching loss. In the semiconductor device, when a two-dimensional shape on a main surface of the semiconductor substrate is an unit cell, the shape being a repeating unit of a plurality of well regions periodically disposed in a surface layer of a drift layer, one unit cell and another unit cell adjacent in an x-axis direction are disposed misaligned in a y-axis direction, and one unit cell and another unit cell adjacent in the y-axis direction are disposed misaligned in the x-axis direction.

Abstract: A power semiconductor device includes a second conductive type sense outer-peripheral well formed to surround a plurality of sense wells on the surface of a drift layer, a first conductive type main-cell source region selectively formed on the surface of the main cell well, a first conductive type sense source region selectively formed on the surface of the sense well, a first conductive type capacitor lower electrode region selectively formed on the surface of the sense outer-peripheral well, a gate insulation film formed on the channel regions and on the sense outer-peripheral well, a gate electrode formed on the gate insulation film, and a sense pad electrically connected to the sense well and the sense source region as well as on the sense outer-peripheral well and the capacitor lower electrode region.