Abstract: In order to realize a wider bandwidth of a frequency characteristic of a power amplification circuit, outputs of differential push-pull amplifiers which are matched at respectively different frequencies are combined together by secondary inductors, and the combined signal is outputted.

Abstract: A power amplifier amplifying and compositing differential signals and capable of suppressing harmonics is provided. The power amplifier includes first amplifiers amplifying a first input signal and a second input signal, which are differential signals, a first coil receiving the first input signal and the second input signal amplified by the first amplifiers, a second coil magnetically coupled with the first coil and outputting a composite signal of the amplified first input signal and second input signal, a third coil magnetically coupled with the second coil, and a first capacitor coupled between both ends of the third coil, wherein one end of the first capacitor is coupled to a ground node.

Abstract: A power amplifier comprises a plurality of primary inductors provided on a substrate in a circular geometry as a whole; a plurality of amplifier pairs; a secondary inductor; and a connection wiring. Each amplifier pair is coupled to two ends of a corresponding primary inductor, and amplifies and output to the corresponding primary inductor a pair of first and second signals given as differential input signals, respectively. The secondary inductor is provided adjacent to the primary inductors in a circular geometry, further combines and outputs signals made by combining first and second signals in each primary inductor. The connection wiring is provided inside the primary inductors on the substrate and electrically couples middle points of respective primary inductors with each other.

Abstract: In order to realize a wider bandwidth of a frequency characteristic of a power amplification circuit, outputs of differential push-pull amplifiers which are matched at respectively different frequencies are combined together by secondary inductors, and the combined signal is outputted.

Abstract: A power amplifier amplifying and compositing differential signals and capable of suppressing harmonics is provided. The power amplifier includes first amplifiers amplifying a first input signal and a second input signal, which are differential signals, a first coil receiving the first input signal and the second input signal amplified by the first amplifiers, a second coil magnetically coupled with the first coil and outputting a composite signal of the amplified first input signal and second input signal, a third coil magnetically coupled with the second coil, and a first capacitor coupled between both ends of the third coil, wherein one end of the first capacitor is coupled to a ground node.

Abstract: In a semiconductor device having an SOI structure and a method of manufacturing the same, influence by a parasitic transistor can be prevented, and no disadvantage is caused in connection with a manufacturing process. In this semiconductor device, an upper side portion of a semiconductor layer is rounded. Thereby, concentration of an electric field at the upper side portion of the semiconductor layer can be prevented. As a result, lowering of a threshold voltage of a parasitic transistor can be prevented, so that the parasitic transistor does not adversely affect subthreshold characteristics of a regular transistor. Owing to provision of a concavity of a U-shaped section, generation of etching residue can be prevented when etching a gate electrode for patterning the same. Thereby, a disadvantage is not caused in connection with the manufacturing process.

Abstract: In a semiconductor device having an SOI structure and a method of manufacturing the same, influence by a parasitic transistor can be prevented, and no disadvantage is caused in connection with a manufacturing process. In this semiconductor device, an upper side portion of a semiconductor layer is rounded. Thereby, concentration of an electric field at the upper side portion of the semiconductor layer can be prevented. As a result, lowering of a threshold voltage of a parasitic transistor can be prevented, so that the parasitic transistor does not adversely affect subthreshold characteristics of a regular transistor. Owing to provision of a concavity of a U-shaped section, generation of etching residue can be prevented when etching a gate electrode for patterning the same. Thereby, a disadvantage is not caused in connection with the manufacturing process.

Abstract: The present invention is to provide a viscous preparation for dental use which comprises basic fibroblast growth factor (bFGF) as an effective ingredient, and further a thickener; a kit for preparing the viscous preparation for dental use; and a method for preparing the viscous preparation for dental use.

Abstract: In a semiconductor device having an SOI structure and a method of manufacturing the same, influence by a parasitic transistor can be prevented, and no disadvantage is caused in connection with a manufacturing process. In this semiconductor device, an upper side portion of a semiconductor layer is rounded. Thereby, concentration of an electric field at the upper side portion of the semiconductor layer can be prevented. As a result, lowering of a threshold voltage of a parasitic transistor can be prevented, so that the parasitic transistor does not adversely affect subthreshold characteristics of a regular transistor. Owing to provision of a concavity of a U-shaped section, generation of etching residue can be prevented when etching a gate electrode for patterning the same. Thereby, a disadvantage is not caused in connection with the manufacturing process.

Abstract: A semiconductor integrated circuit device includes a silicon substrate having a first region and a second region identical in conductivity type to the first region and having a lower dopant concentration than the first region, a second MOS transistor on a main surface of the second region as a radio frequency switch circuit switching on and off input and output of a radio frequency signal, and a first MOS transistor on a main surface of the first region in a radio frequency circuit other than the radio frequency switch circuit. A high performance, highly reliable semiconductor integrated circuit with an RE switch circuit provided on a silicon substrate as a system on a chip.

Abstract: In a semiconductor device having an SOI structure and a method of manufacturing the same, influence by a parasitic transistor can be prevented, and no disadvantage is caused in connection with a manufacturing process. In this semiconductor device, an upper side portion of a semiconductor layer is rounded. Thereby, concentration of an electric field at the upper side portion of the semiconductor layer can be prevented. As a result, lowering of a threshold voltage of a parasitic transistor can be prevented, so that the parasitic transistor does not adversely affect subthreshold characteristics of a regular transistor. Owing to provision of a concavity of a U-shaped section, generation of etching residue can be prevented when etching a gate electrode for patterning the same. Thereby, a disadvantage is not caused in connection with the manufacturing process.

Abstract: In a semiconductor device having an SOI structure and a method of manufacturing the same, influence by a parasitic transistor can be prevented, and no disadvantage is caused in connection with a manufacturing process. In this semiconductor device, an upper side portion of a semiconductor layer is rounded. Thereby, concentration of an electric field at the upper side portion of the semiconductor layer can be prevented. As a result, lowering of a threshold voltage of a parasitic transistor can be prevented, so that the parasitic transistor does not adversely affect subthreshold characteristics of a regular transistor. Owing to provision of a concavity of a U-shaped section, generation of etching residue can be prevented when etching a gate electrode for patterning the same. Thereby, a disadvantage is not caused in connection with the manufacturing process.

Abstract: A semiconductor integrated circuit device includes a silicon substrate having a first region and a second region identical in conductivity to said first region and having a lower dopant concentration than said first region, a second MOS transistor formed on a main surface of said second region and configuring a radio frequency switch circuit switching on/off an input and output of a radio frequency signal, and a first MOS transistor formed on a main surface of said first region and configuring a radio frequency circuit other than said radio frequency switch circuit. There can be provided a high performance, highly reliable semiconductor integrated circuit with an RF switch circuit provided on a silicon substrate by SOPing.

Abstract: In a semiconductor device having an SOI structure and a method of manufacturing the same, influence by a parasitic transistor can be prevented, and no disadvantage is caused in connection with a manufacturing process. In this semiconductor device, an upper side portion of a semiconductor layer is rounded. Thereby, concentration of an electric field at the upper side portion of the semiconductor layer can be prevented. As a result, lowering of a threshold voltage of a parasitic transistor can be prevented, so that the parasitic transistor does not adversely affect subthreshold characteristics of a regular transistor. Owing to provision of a concavity of a U-shaped section, generation of etching residue can be prevented when etching a gate electrode for patterning the same. Thereby, a disadvantage is not caused in connection with the manufacturing process.

Abstract: A method of manufacturing a semiconductor device is provided in which a semiconductor device including a plurality of FETs having different threshold voltages and gate insulating films with different film thicknesses can be manufactured in a simplified process. Specifically, a first gate insulating film is formed on the main surface of a semiconductor substrate. On the first gate insulating film, a first protection film is formed. In regions A and B in each of which an FET having a second gate insulating film with a film thickness different from that of the first gate insulating film is to be formed, the first gate insulating film and the first protection film are removed to expose the surface of the semiconductor substrate. At the same time, the first protection film is left in regions other than the regions A and B. Using the first protection film as a mask, an impurity is implanted into the semiconductor substrate in the regions A and B.

Abstract: In a semiconductor device having an SOI structure and a method of manufacturing the same, influence by a parasitic transistor can be prevented, and no disadvantage is caused in connection with a manufacturing process. In this semiconductor device, an upper side portion of a semiconductor layer is rounded. Thereby, concentration of an electric field at the upper side portion of the semiconductor layer can be prevented. As a result, lowering of a threshold voltage of a parasitic transistor can be prevented, so that the parasitic transistor does not adversely affect subthreshold characteristics of a regular transistor. Owing to provision of a concavity of a U-shaped section, generation of etching residue can be prevented when etching a gate electrode for patterning the same. Thereby, a disadvantage is not caused in connection with the manufacturing process.

Abstract: A thin film forming apparatus using laser includes a chamber (1), a target (5) placed therein, a laser light source (10) for emitting laser beam to target (5), and a substrate holder (3). When target (5) is irradiated with laser beam (16), a plume (15) is generated, and materials included in plume (15) are deposited on the surface of a substrate (2) held by substrate holder (3). The laser beam emitted from laser light source (10) has its cross section shaped to a desired shape when passed through a shielding plate (4804), for example, so that the surface of the target (5) is irradiated with the beam having uniform light intensity distribution. Therefore, a plume (15) having uniform density distribution of active particles is generated, and therefore a thin film of high quality can be formed over a wide area with uniform film quality, without damaging the substrate.

Abstract: In a semiconductor device having an SOI structure and a method of manufacturing the same, influence by a parasitic transistor can be prevented, and no disadvantage is caused in connection with a manufacturing process. In this semiconductor device, an upper side portion of a semiconductor layer is rounded. Thereby, concentration of an electric field at the upper side portion of the semiconductor layer can be prevented. As a result, lowering of a threshold voltage of a parasitic transistor can be prevented, so that the parasitic transistor does not adversely affect subthreshold characteristics of a regular transistor. Owing to provision of a concavity of a U-shaped section, generation of etching residue can be prevented when etching a gate electrode for patterning the same. Thereby, a disadvantage is not caused in connection with the manufacturing process.

Abstract: A thin film forming apparatus using laser includes a chamber (1), a target (5) placed therein, a laser light source (10) for emitting laser beam to target (5), and a substrate holder (3). When target (5) is irradiated with laser beam (16), a plume (15) is generated, and materials included in plume (15) are deposited on the surface of a substrate (2) held by substrate holder (3). The laser beam emitted from laser light source (10) has its cross section shaped to a desired shape when passed through a shielding plate (4804), for example, so that the surface of the target (5) is irradiated with the beam having uniform light intensity distribution. Therefore, a plume (15) having uniform density distribution of active particles is generated, and therefore a thin film of high quality can be formed over a wide area with uniform film quality, without damaging the substrate.

Abstract: A photo-assisted CVD apparatus including a reaction chamber for storing a substrate, an inlet port for feeding a source gas into the reaction chamber, a light source for radiating light on the source gas fed into the reaction chamber to decompose the source gas upon radiating the light, thereby depositing a film on the substrate, an inlet port for supplying an etching gas into the reaction chamber, and a discharge electrode, arranged above the substrate and having a configuration, surrounding a space above the substrate, for exciting the etching gas.