Abstract: In one embodiment of the present invention, a frame interpolation process circuit performs an interpolation process on a video signal in units of frames. A time-division gradation process circuit performs gradation level conversion for distributing brightness for one frame cycle to two sub-frame cycles, i.e., first and second sub-frame cycles. A gradation level change detection circuit detects whether a gradation level of each pixel has changed between consecutive sub-frames. For any pixel having its gradation level changed, an overshoot process circuit outputs, instead of an output signal of the time-division gradation process circuit, a video signal obtained by subjecting an output signal of the frame interpolation process circuit to gradation level conversion for emphasizing a temporal change of the signal. A predetermined-times higher speed process circuit may be added to this circuit configuration, or may be substituted for the frame interpolation process circuit.

Abstract: A two-dimensional filter arithmetic device comprises a picture memory (300), a line memory (400), a vertical filtering unit (100) which includes nine first filter modules installed in parallel, a buffer (500) for timing adjustments, and a horizontal filtering unit (200) which includes four second filter modules installed in parallel. From the line memory (400), the pixel values of nine full pels per line are inputted in parallel to the vertical filtering unit (100), nine vertically-filtered values of half pels are generated and inputted to the horizontal filtering unit (200); thereby, four two-dimensionally-filtered values of half pels are generated.

Abstract: There is a problem of increasing image quality deterioration when selection of an intra prediction mode for a face outline portion is not correct at a low bit-rate. This invention includes: a face detection unit detecting a face image from an input picture; and an intra prediction mode control unit controlling intra prediction mode selection based on a result of the detection of the face detection unit. In the control of intra prediction mode selection, an intra prediction mode is selected based on where a current block is positioned in a region of the face image. Thereby, an appropriate intra prediction mode can be selected for the face outline portion. As a result, image quality deterioration on the face image at a low bit-rate can be prevented.

Abstract: A simple double-speed process circuit 60 outputs a video signal V1 twice at a double speed in units of frames. A time-division gradation process circuit 50 performs gradation level conversion on the video signal in order to distribute brightness for one frame cycle to two sub-frame cycles, i.e. first and second sub-frame cycles. An overshoot process circuit 40 performs gradation level conversion on the video signal in order to-emphasize a temporal change of the signal. A drive circuit 20 drives liquid crystal display elements 31 using a video signal V2 obtained through processing by the three circuits. A frame interpolation process circuit may be added to this circuit configuration or may be substituted for the simple double-speed process circuit 60. This makes it possible to improve moving image display performance, while making up for a lack of response speed of the display elements.

Abstract: In the first display mode, a first tone converting circuit and a second tone converting circuit of a control LSI divide one frame period of an input image signal into a plurality of sub-frame periods to perform output to a display panel, thus realizing image display performed by time-division driving (pseudo-impulse driving). In the second display mode, the control LSI directly outputs an input image signal to the display panel, thus realizing image display performed by hold driving. In at least one embodiment, switching between the first display mode and the second display mode is performed by changing output of an output data selector according to a mode switching signal. This realizes an image display apparatus which effectively obtains the effect of suppressing blurring of a moving image and alleviates the problem of flickers caused by pseudo-impulse driving.

Abstract: An liquid crystal display (LCD) device uses a method for displaying halftone without causing luminance differences among pixels when an FRC technique is used, and without causing stripe-shaped luminance variations when a flicker component is eliminated spatially. The LCD device includes a data splitter, a pixel location detecting circuit, a frame number determining circuit, an applied timing memory circuit, an applied voltage determining circuit, a summation process circuit, and a timing adjusting circuit. The LCD device determines driving voltages such that for each of a high voltage or a low voltage during these 2N frames, the number of applying positive voltages is the same as the number of applying negative voltages where a unit period is 2N frames for multi-gray-level display of (1+N) levels. The LCD device can improve image quality since the average luminance of each pixel is made uniform.

Abstract: A portable terminal including an input unit (1001), through which images are entered, an encoding unit (1002) operable to encode the input images, thereby providing encoded data, a transmitting unit (1003) operable to transmit the encoded data to a communication counterpart, a receiving unit (1006) operable to receive communication counterpart-related information from the communication counterpart, and a mode-determining unit operable to determine an encoding method. The mode-determining unit receives the information on each of the self-terminal and the communication counterpart, thereby providing the determined encoding method. As a result, even when each of the self-terminal and the communication counterpart retains a sufficient level of remaining battery power, the encoding method is properly changed to suppress unwanted power consumption, whereby communication between the self-terminal and the communication counterpart can be made for a longer period of time.

Abstract: A control LSI (30) time-divides one frame period of an input image signal into a plurality of sub-frame periods and outputs the signal to a display panel, so as to carry out image display by pseudo impulse driving. At this time, in a first display mode, a first tone converting circuit (34) refers to a first table (37), and a second tone converting circuit (35) refers to a third table (39), to generate an image signal of each sub-frame from the input image signal. In a second display mode, the first tone converting circuit (34) refers to a second table (38), and the second tone converting circuit (35) refers to a fourth table (40), to generate the image signal of the sub-frame from the input image signal. Each of a first selector (41) and a second selector (42) switches the tables to be referred in accordance with a mode switching signal.

Abstract: An output processing apparatus comprises a first storage that stores image data in a predetermined block unit, a second storage that stores a head address of each of the image data stored in the block units, and a controller that reads, from the first storage, the same line of the image data of the plural continuous blocks on a line-by-line basis based on the head address stored in the second storage, and outputs the plural lines of the readout image data to a recorder as one line of continuous image data.

Abstract: An image decoding device and an image encoding device according to the present invention includes an arithmetic unit for performing arithmetic processing, an arithmetic data storage unit for storing an arithmetic result by the arithmetic unit, an input selection unit for selecting whether to read pixel data that is to be inputted to the arithmetic unit from compressed image data or from pixel data stored in the arithmetic data storage unit, and inputting the read pixel data to the arithmetic unit, and an arithmetic control unit for controlling, based on a transform mode used and the number of arithmetic operations in the arithmetic unit, a destination from which the pixel data that is to be inputted to the arithmetic unit by the input selection unit is read as well as a combination of pieces of pixel data targeted for the arithmetic processing by the arithmetic unit and multiplier coefficients for the arithmetic processing, the arithmetic control unit previously defining an arithmetic procedure in each transf

Abstract: Reference picture data for full-pel-precision motion detection and picture data of a macroblock to be encoded are transferred from an SDRAM (41) to a local memory (31). The full-pel-precision motion detection is performed by a full-pel-precision motion detecting unit (21), and the transfer region of the reference picture data for quarter-pel-precision motion detection is determined based on the result of the full-pel-precision motion detection. After transferring the reference picture data for half-pel-precision motion detection, the half-pel-precision motion detection by a half-pel-precision motion detecting unit 22 and the reference picture data transfer for quarter-pel-precision motion detection are practiced concurrently. The quarter-pel-precision motion detection is practiced by a quarter-pel-precision motion detecting unit (23). Consequently, the pipeline stages and the pipeline buffers can be diminished in number, thereby accelerating the pipeline processing.

Abstract: In a data-sending device, a data generation section provides input data itself or a bit-inverted version of the input data as intermediate data and generates an inversion signal that indicates whether or not the intermediate data is the bit-inverted version of the input data. An encrypting section generates scrambled data by inserting the inversion signal in the intermediate data at a bit position. A data-receiving device removes the inversion signal from the scrambled data, and restores the input data based on the inversion signal.

Abstract: An image display system includes at least one display device connected to a host device. An image is displayed on the at least one display device in accordance with an image signal which is output from the host device. The at least one display device monitors a state of coupling with the host device.

Abstract: A total specification is divided into a hardware specification and a software specification. With respect to the hardware specification, a first hardware description is described. With respect to the software specification, an object program is generated, which is converted into a second hardware description. The first and second hardware descriptions are logically synthesized into a net list, which includes a part that fulfills the software specification. Since the object program is converted into the second hardware description, which is logically synthesized, the redundancy of the program can be removed and cost for manufacturing hardware can be reduced.

Abstract: A power management system for an integrated circuit has a signal line, a management data generating unit connected to the signal line, and a plurality of management data using units each connected to the signal line. The management data generating unit outputs, to the signal line, power management data for managing power consumption in each of the management data using units, the power management data corresponding to the state of the management data generating unit. Each of the management data using units reads the power management data for common use from the signal line and controls power consumed by the management data using unit based on the power management data.

Abstract: A server system of the present invention includes a server apparatus and one or more terminal apparatuses electrically connected to the server apparatus through a transmission line, in which each of the one or more terminal apparatuses include one or more input devices, the server apparatus implements an operating system and an application program, the server apparatus includes input information recognition means for recognizing an input information signal which is output from each of the one or more input devices and input to the server apparatus, and the server apparatus executes the operating system and the application program based on the input information signal.

Abstract: An image display apparatus is provided for performing image display by dividing one frame period into a plurality of sub-frame periods, determining a gradation level of each of the sub-frame periods in accordance with a gradation level of an input image signal and supplying the determined gradation level to an image display section. The image display apparatus comprises a display control section, wherein the display control section supplies a relatively largest gradation level in a relatively central sub-frame period which is at a time-wise center or closest to the time-wise center of one frame period, and supplies a sequentially lowered gradation level in a sub-frame period which is sequentially farther from the relatively central sub-frame period.

Abstract: A surface acoustic wave (SAW) filter includes a SAW chip mounted in a recession of a multi-layer substrate, a sealing plate covering the recession, an end surface electrode that is provided on the outer surface of the substrate and is in conduction with the SAW chip, a metal conductor for radiating heat that is provided on the surface at the opposite side from the sealing plate of the multi-layer substrate, and a through hole provided in the substrate, one end thereof being connected to the metal conductor. The other end of the through hole is connected with the SAW chip through the intermediary of a metal constituent, such as an electrically conductive adhesive layer.

Abstract: A synchronization signal generation circuit includes: a synchronization signal generation section for generating a first vertical synchronization signal and a first horizontal synchronization signal based on an externally-supplied second vertical synchronization signal; and a detection section for detecting the second vertical synchronization signal, wherein when the second vertical synchronization signal is detected by the detection section for the first time, the first vertical synchronization signal is not output by the synchronization signal generation section, and when the second vertical synchronization signal is detected by the detection section for the next time at a predetermined timing, the first vertical synchronization signal is output by the synchronization signal generation section.

Abstract: An liquid crystal display (LCD) device uses a method for displaying halftone without causing luminance differences among pixels when an FRC technique is used, and without causing stripe-shaped luminance variations when a flicker component is eliminated spatially. The LCD device includes a data splitter, a pixel location detecting circuit, a frame number determining circuit, an applied timing memory circuit, an applied voltage determining circuit, a summation process circuit, and a timing adjusting circuit. The LCD device determines driving voltages such that for each of a high voltage or a low voltage during these 2N frames, the number of applying positive voltages is the same as the number of applying negative voltages where a unit period is 2N frames for multi-gray-level display of (1+N) levels. The LCD device can improve image quality since the average luminance of each pixel is made uniform.