Patents by Inventor Akihiko Yoshioka
Akihiko Yoshioka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240117384Abstract: Provided is a method for altering a targeted site of a DNA in a cell, including a step of stimulating the cell with a factor inducing a DNA modifying enzyme endogenous to the cell, and bringing a complex of a nucleic acid sequence-recognizing module specifically binding to a target nucleotide sequence in a given DNA and a DNA modifying enzyme-binding module bonded to each other into contact with the DNA to convert one or more nucleotides in the targeted site to other one or more nucleotides or delete one or more nucleotides, or insert one or more nucleotides into the targeted site.Type: ApplicationFiled: December 14, 2023Publication date: April 11, 2024Applicant: NATIONAL UNIVERSITY CORPORATION KOBE UNIVERSITYInventors: Keiji NISHIDA, Akihiko KONDO, Takayuki ARAZOE, Shin YOSHIOKA
-
Publication number: 20240069280Abstract: A photodetector includes a substrate, a material layer, a first electrode made of a metal, a core, a second electrode and a light absorption layer made of graphene. The first electrode, the core, and the material layer constitute a hybrid plasmonic waveguide, and the light absorption layer is disposed thereon. Light guided in the hybrid plasmonic waveguide is absorbed by the light absorption layer, photoelectrically converted by the PTE effect, and extracted as an electric signal from the first electrode and the second electrode.Type: ApplicationFiled: February 8, 2021Publication date: February 29, 2024Inventors: Masaaki Ono, Katsumasa Yoshioka, Kengo Nozaki, Akihiko Shinya, Masaya Notomi
-
Patent number: 10957719Abstract: A semiconductor device manufacturing technique which allows reduction of semiconductor chip size. First, a pad and other wires are formed over an insulating film. A surface protective film is formed over the insulating film including the pad and wires, and an opening is made in the surface protective film. The opening lies over the pad and exposes a surface of the pad. A bump electrode is formed over the surface protective film including the opening. Here, the pad is smaller than the bump electrode. Consequently, the wires are arranged just beneath the bump electrode in the same layer as the pad 10. In other words, the wires are arranged in space which becomes available because the pad is small enough.Type: GrantFiled: April 7, 2020Date of Patent: March 23, 2021Assignee: Renesas Electronics CorporationInventors: Akihiko Yoshioka, Shinya Suzuki
-
Publication number: 20200235131Abstract: A semiconductor device manufacturing technique which allows reduction of semiconductor chip size. First, a pad and other wires are formed over an insulating film. A surface protective film is formed over the insulating film including the pad and wires, and an opening is made in the surface protective film. The opening lies over the pad and exposes a surface of the pad. A bump electrode is formed over the surface protective film including the opening. Here, the pad is smaller than the bump electrode. Consequently, the wires are arranged just beneath the bump electrode in the same layer as the pad 10. In other words, the wires are arranged in space which becomes available because the pad is small enough.Type: ApplicationFiled: April 7, 2020Publication date: July 23, 2020Inventors: Akihiko YOSHIOKA, Shinya SUZUKI
-
Patent number: 10411095Abstract: A semiconductor integrated circuit includes a first conduction-type semiconductor region, a second conduction-type first impurity region, and a guard ring formed using a first conduction-type second impurity region so as to form a protection device of an electrostatic protection circuit. The first impurity region is formed inside the semiconductor region to have a rectangular planar structure with long and short sides. The guard ring is formed inside the semiconductor region to surround the periphery of the first impurity region. A weak spot is formed on the short side of the rectangular planar structure of the first impurity region. A plurality of electrical contacts are formed in a first portion of the guard ring which faces the long side of the rectangle. A plurality of electrical contracts are not formed in a second portion of the guard ring which faces the weak spot formed on the short side of the rectangle.Type: GrantFiled: March 14, 2018Date of Patent: September 10, 2019Assignee: Renesas Electronics CorporationInventor: Akihiko Yoshioka
-
Publication number: 20190244978Abstract: A semiconductor device manufacturing technique which allows reduction of semiconductor chip size. First, a pad and other wires are formed over an insulating film. A surface protective film is formed over the insulating film including the pad and wires, and an opening is made in the surface protective film. The opening lies over the pad and exposes a surface of the pad. A bump electrode is formed over the surface protective film including the opening. Here, the pad is smaller than the bump electrode. Consequently, the wires are arranged just beneath the bump electrode in the same layer as the pad 10. In other words, the wires are arranged in space which becomes available because the pad is small enough.Type: ApplicationFiled: April 16, 2019Publication date: August 8, 2019Inventors: Akihiko YOSHIOKA, Shinya SUZUKI
-
Patent number: 10304867Abstract: A semiconductor device manufacturing technique which allows reduction of semiconductor chip size. First, a pad and other wires are formed over an insulating film. A surface protective film is formed over the insulating film including the pad and wires, and an opening is made in the surface protective film. The opening lies over the pad and exposes a surface of the pad. A bump electrode is formed over the surface protective film including the opening. Here, the pad is smaller than the bump electrode. Consequently, the wires are arranged just beneath the bump electrode in the same layer as the pad 10. In other words, the wires are arranged in space which becomes available because the pad is small enough.Type: GrantFiled: February 19, 2018Date of Patent: May 28, 2019Assignee: Renesas Electronics CorporationInventors: Akihiko Yoshioka, Shinya Suzuki
-
Publication number: 20180277633Abstract: A semiconductor integrated circuit includes a first conduction-type semiconductor region, a second conduction-type first impurity region, and a guard ring formed using a first conduction-type second impurity region so as to form a protection device of an electrostatic protection circuit. The first impurity region is formed inside the semiconductor region to have a rectangular planar structure with long and short sides. The guard ring is formed inside the semiconductor region to surround the periphery of the first impurity region. A weak spot is formed on the short side of the rectangular planar structure of the first impurity region. A plurality of electrical contacts are formed in a first portion of the guard ring which faces the long side of the rectangle. A plurality of electrical contracts are not formed in a second portion of the guard ring which faces the weak spot formed on the short side of the rectangle.Type: ApplicationFiled: March 14, 2018Publication date: September 27, 2018Inventor: Akihiko YOSHIOKA
-
Publication number: 20180175067Abstract: A semiconductor device manufacturing technique which allows reduction of semiconductor chip size. First, a pad and other wires are formed over an insulating film. A surface protective film is formed over the insulating film including the pad and wires, and an opening is made in the surface protective film. The opening lies over the pad and exposes a surface of the pad. A bump electrode is formed over the surface protective film including the opening. Here, the pad is smaller than the bump electrode. Consequently, the wires are arranged just beneath the bump electrode in the same layer as the pad 10. In other words, the wires are arranged in space which becomes available because the pad is small enough.Type: ApplicationFiled: February 19, 2018Publication date: June 21, 2018Inventors: Akihiko YOSHIOKA, Shinya SUZUKI
-
Patent number: 9941358Abstract: A semiconductor integrated circuit includes a first conduction-type semiconductor region, a second conduction-type first impurity region, and a guard ring formed using a first conduction-type second impurity region so as to form a protection device of an electrostatic protection circuit. The first impurity region is formed inside the semiconductor region to have a rectangular planar structure with long and short sides. The guard ring is formed inside the semiconductor region to surround the periphery of the first impurity region. A weak spot is formed on the short side of the rectangular planar structure of the first impurity region. A plurality of electrical contacts are formed in a first portion of the guard ring which faces the long side of the rectangle. A plurality of electrical contracts are not formed in a second portion of the guard ring which faces the weak spot formed on the short side of the rectangle.Type: GrantFiled: July 25, 2012Date of Patent: April 10, 2018Assignee: Renesas Electronics CorporationInventor: Akihiko Yoshioka
-
Patent number: 9929185Abstract: A semiconductor device manufacturing technique which allows reduction of semiconductor chip size. First, a pad and other wires are formed over an insulating film. A surface protective film is formed over the insulating film including the pad and wires, and an opening is made in the surface protective film. The opening lies over the pad and exposes a surface of the pad. A bump electrode is formed over the surface protective film including the opening. Here, the pad is smaller than the bump electrode. Consequently, the wires are arranged just beneath the bump electrode in the same layer as the pad 10. In other words, the wires are arranged in space which becomes available because the pad is small enough.Type: GrantFiled: December 1, 2016Date of Patent: March 27, 2018Assignee: Renesas Electronics CorporationInventors: Akihiko Yoshioka, Shinya Suzuki
-
Publication number: 20170084633Abstract: A semiconductor device manufacturing technique which allows reduction of semiconductor chip size. First, a pad and other wires are formed over an insulating film. A surface protective film is formed over the insulating film including the pad and wires, and an opening is made in the surface protective film. The opening lies over the pad and exposes a surface of the pad. A bump electrode is formed over the surface protective film including the opening. Here, the pad is smaller than the bump electrode. Consequently, the wires are arranged just beneath the bump electrode in the same layer as the pad 10. In other words, the wires are arranged in space which becomes available because the pad is small enough.Type: ApplicationFiled: December 1, 2016Publication date: March 23, 2017Inventors: Akihiko YOSHIOKA, Shinya SUZUKI
-
Patent number: 9576924Abstract: A semiconductor device manufacturing technique which allows reduction of semiconductor chip size. First, a pad and other wires are formed over an insulating film. A surface protective film is formed over the insulating film including the pad and wires, and an opening is made in the surface protective film. The opening lies over the pad and exposes a surface of the pad. A bump electrode is formed over the surface protective film including the opening. Here, the pad is smaller than the bump electrode. Consequently, the wires are arranged just beneath the bump electrode in the same layer as the pad 10. In other words, the wires are arranged in space which becomes available because the pad is small enough.Type: GrantFiled: August 26, 2015Date of Patent: February 21, 2017Assignee: Renesas Electronics CorporationInventors: Akihiko Yoshioka, Shinya Suzuki
-
Publication number: 20150364437Abstract: A semiconductor device manufacturing technique which allows reduction of semiconductor chip size. First, a pad and other wires are formed over an insulating film. A surface protective film is formed over the insulating film including the pad and wires, and an opening is made in the surface protective film. The opening lies over the pad and exposes a surface of the pad. A bump electrode is formed over the surface protective film including the opening. Here, the pad is smaller than the bump electrode. Consequently, the wires are arranged just beneath the bump electrode in the same layer as the pad 10. In other words, the wires are arranged in space which becomes available because the pad is small enough.Type: ApplicationFiled: August 26, 2015Publication date: December 17, 2015Inventors: Akihiko Yoshioka, Shinya Suzuki
-
Patent number: 9159650Abstract: A semiconductor device manufacturing technique which allows reduction of semiconductor chip size. First, a pad and other wires are formed over an insulating film. A surface protective film is formed over the insulating film including the pad and wires, and an opening is made in the surface protective film. The opening lies over the pad and exposes a surface of the pad. A bump electrode is formed over the surface protective film including the opening. Here, the pad is smaller than the bump electrode. Consequently, the wires are arranged just beneath the bump electrode in the same layer as the pad 10. In other words, the wires are arranged in space which becomes available because the pad is small enough.Type: GrantFiled: December 17, 2013Date of Patent: October 13, 2015Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Akihiko Yoshioka, Shinya Suzuki
-
Publication number: 20140103525Abstract: A semiconductor device manufacturing technique which allows reduction of semiconductor chip size. First, a pad and other wires are formed over an insulating film. A surface protective film is formed over the insulating film including the pad and wires, and an opening is made in the surface protective film. The opening lies over the pad and exposes a surface of the pad. A bump electrode is formed over the surface protective film including the opening. Here, the pad is smaller than the bump electrode. Consequently, the wires are arranged just beneath the bump electrode in the same layer as the pad 10. In other words, the wires are arranged in space which becomes available because the pad is small enough.Type: ApplicationFiled: December 17, 2013Publication date: April 17, 2014Applicant: Renesas Electronics CorporationInventors: Akihiko Yoshioka, Shinya Suzuki
-
Patent number: 8624403Abstract: A semiconductor device manufacturing technique which allows reduction of semiconductor chip size. First, a pad and other wires are formed over an insulating film. A surface protective film is formed over the insulating film including the pad and wires, and an opening is made in the surface protective film. The opening lies over the pad and exposes a surface of the pad. A bump electrode is formed over the surface protective film including the opening. Here, the pad is smaller than the bump electrode. Consequently, the wires are arranged just beneath the bump electrode in the same layer as the pad 10. In other words, the wires are arranged in space which becomes available because the pad is small enough.Type: GrantFiled: November 20, 2012Date of Patent: January 7, 2014Assignee: Renesas Electronics CorporationInventors: Akihiko Yoshioka, Shinya Suzuki
-
Patent number: 8525824Abstract: There is provided a display driver device (liquid crystal driver) causing no degradation in display image quality even when a plurality of signal lines (source lines) of a display panel are divided into a plurality of groups as a countermeasure against EMI. With a liquid crystal display driver device (the liquid crystal driver) for generating image signals to be impressed to respective signal lines of a display panel upon receiving display image data, and outputting the image signals in a lump, corresponding to every one line, according to an output timing signal inputted from outside, output amplifiers, in the last stage of the liquid crystal driver, for outputting the image signals, respectively, are divided into a plurality of groups, and the output amplifiers of respective groups are caused to undergo a periodical change in output sequence while the respective image signals are slightly staggered in output timing by the group.Type: GrantFiled: February 18, 2010Date of Patent: September 3, 2013Assignee: Renesas Electronics CorporationInventors: Kazuhiro Okamura, Akihiko Yoshioka
-
Publication number: 20130026550Abstract: A semiconductor integrated circuit includes a first conduction-type semiconductor region, a second conduction-type first impurity region, and a guard ring formed using a first conduction-type second impurity region so as to form a protection device of an electrostatic protection circuit. The first impurity region is formed inside the semiconductor region to have a rectangular planar structure with long and short sides. The guard ring is formed inside the semiconductor region to surround the periphery of the first impurity region. A weak spot is formed on the short side of the rectangular planar structure of the first impurity region. A plurality of electrical contacts are formed in a first portion of the guard ring which faces the long side of the rectangle. A plurality of electrical contracts are not formed in a second portion of the guard ring which faces the weak spot formed on the short side of the rectangle.Type: ApplicationFiled: July 25, 2012Publication date: January 31, 2013Inventor: Akihiko YOSHIOKA
-
Patent number: 8338968Abstract: A semiconductor device manufacturing technique which allows reduction of semiconductor chip size. First, a pad and other wires are formed over an insulating film. A surface protective film is formed over the insulating film including the pad and wires, and an opening is made in the surface protective film. The opening lies over the pad and exposes a surface of the pad. A bump electrode is formed over the surface protective film including the opening. Here, the pad is smaller than the bump electrode. Consequently, the wires are arranged just beneath the bump electrode in the same layer as the pad 10. In other words, the wires are arranged in space which becomes available because the pad is small enough.Type: GrantFiled: February 14, 2012Date of Patent: December 25, 2012Assignee: Renesas Electronics CorporationInventors: Akihiko Yoshioka, Shinya Suzuki