Abstract: A diaphragm 10 is fixed to a base plate 102 by a screw 13. A lever 20 has a spring member 23, a rotor-fixing member 25, and an insertion hole 22 formed therein. By passing a shaft 21 through the insertion hole 22, the lever 20 is turnably supported so as to turn about its own axis. In a state in which the spring member 23 abuts against an eccentric pressure-adjusting cam 26, a pressing force for urging the diaphragm 10 via the rotor 100 is adjusted by turning the pressure-adjusting cam 26 so as to change an elastic force of the spring member 23.

Abstract: In a voltage-controlled oscillator, a second variable capacitor circuit is provided in a variable capacitor circuit group, in addition to a first variable capacitor circuit having a first variable capacitor whose capacitance varies continuously in accordance with a frequency control signal. The second variable capacitor circuit has several second variable capacitors whose capacitances vary continuously in accordance with the frequency control signal and switching circuits that select the second variable capacitors in accordance with frequency band control signals. The oscillation frequency is changed only with the first variable capacitor in higher oscillation frequency bands. When the oscillation frequency is in lower oscillation frequency bands, the oscillation frequency band is changed also with the second variable capacitors. Accordingly, it is possible to ensure broad oscillation frequency bands, while reducing variations in the VCO gain in the entire oscillation frequency bands to a low level.

Abstract: An electronic timepiece without system failure at the time of transfer from the power-saving mode to the display mode is provided. A power-saving control circuit 400 controls drive of a date dial displaying a date when updating a date display, which has been stopped in a power-saving mode, to a current date at the time of transfer from the power-saving mode to the display mode. The power-saving control circuit 400 outputs a date dial drive inhibiting signal, which prohibits drive of the date dial 75, to a date-updating control circuit 300, if a voltage VDD of a power source unit B is less than or equal to a low threshold voltage V1. It outputs a date dial deceleration driving signal, which drives a date dial 75 with a predetermined speed slower than a normal update speed when transferring to the display mode, to a date-updating control circuit 300, if a source voltage VDD is equal to or less than a high threshold voltage V2.

Abstract: A piezoactuator has a diaphragm, and the diaphragm has flat piezoelectric elements that oscillate in a longitudinal oscillation mode and a sinusoidal oscillation mode. A first electrode for detecting oscillation in the longitudinal oscillation mode, and a second electrode for detecting the amplitude of oscillation in the sinusoidal oscillation mode, are disposed on the surface of the diaphragm. When the piezoactuator is driven with a drive signal, the phase difference of a first detection signal output from the first electrode and a second detection signal output from the second electrode is detected. The frequency at which the detected phase difference becomes the maximum phase difference is then obtained, and a drive signal of a matching frequency is applied to the piezoelectric elements.

Abstract: A data processing device and method permit improved display of data and characters on a display. When an enlargement display key is input after designating characters, a line or block, on the enlargement display flag signal is indicated. The device and method permit the displayed data to be have its size increased on a display screen so as to be equal to the size to be printed. However, if the size to be printed is too small to be clearly viewed, the data on the display screen can be enlarged and an appropriate signal is displayed on the display.

Abstract: In a driver circuit for driving a pair of data lines, the amplitude of a differential input signal is reduced from 2.5 V to 0.6 V, which is smaller than a conventional lower-limit source voltage (approximately 1.5 V). The amplitude of the differential signal transmitted through the pair of data lines is amplified to 2.5 V by an amplifying circuit and the resulting signal is then latched by a latch circuit. After the latching by the latch circuit, the operation of the amplifying circuit is halted. The driver circuit is constituted solely by a plurality of NMOS transistors so as not to increase a leakage current flowing in the off state. Here, the threshold voltage of the NMOS transistor positioned on the ground side is reduced to a conventional lower-limit value (0.3 V to 0.6 V), while the threshold voltage of the NMOS transistor on the power-source side to a value lower than the above lower-limit value (0 V to 0.3 V), thereby enhancing a driving force of the NMOS transistor on the power-source side.

Abstract: In a driver circuit for driving a pair of data lines, the amplitude of a differential input signal is reduced from 2.5 V to 0.6 V, which is smaller than a conventional lower-limit source voltage (approximately 1.5 V). The amplitude of the differential signal transmitted through the pair of data lines is amplified to 2.5 V by an amplifying circuit and the resulting signal is then latched by a latch circuit. After the latching by the latch circuit, the operation of the amplifying circuit is halted. The driver circuit is constituted solely by a plurality of NMOS transistors so as not to increase a leakage current flowing in the off state. Here, the threshold voltage of the NMOS transistor positioned on the ground side is reduced to a conventional lower-limit value (0.3 V to 0.6 V), while the threshold voltage of the NMOS transistor on the power-source side to a value lower than the above lower-limit value (0 V to 0.3 V), thereby enhancing a driving force of the NMOS transistor on the power-source side.

Abstract: In a driver circuit for driving a pair of data lines, the amplitude of a differential input signal is reduced from 2.5 V to 0.6 V, which is smaller than a conventional lower-limit source voltage (approximately 1.5 V). The amplitude of the differential signal transmitted through the pair of data lines is amplified to 2.5 V by an amplifying circuit and the resulting signal is then latched by a latch circuit. After the latching by the latch circuit, the operation of the amplifying circuit is halted. The driver circuit is constituted solely by a plurality of NMOS transistors so as not to increase a leakage current flowing in the off state. Here, the threshold voltage of the NMOS transistor positioned on the ground side is reduced to a conventional lower-limit value (0.3 V to 0.6 V), while the threshold voltage of the NMOS transistor on the power-source side to a value lower than the above lower-limit value (0 V to 0.3 V), thereby enhancing a driving force of the NMOS transistor on the power-source side.

Abstract: In a driver circuit for driving a pair of data lines, the amplitude of a differential input signal is reduced from 2.5 V to 0.6 V, which is smaller than a conventional lower-limit source voltage (approximately 1.5 V). The amplitude of the differential signal transmitted through the pair of data lines is amplified to 2.5 V by an amplifying circuit and the resulting signal is then latched by a latch circuit. After the latching by the latch circuit, the operation of the amplifying circuit is halted. The driver circuit is constituted solely by a plurality of NMOS transistors so as not to increase a leakage current flowing in the off state. Here, the threshold voltage of the NMOS transistor positioned on the ground side is reduced to a conventional lower-limit value (0.3 V to 0.6 V), while the threshold voltage of the NMOS transistor on the power-source side to a value lower than the above lower-limit value (0 V to 0.3 V), thereby enhancing a driving force of the NMOS transistor on the power-source side.

Abstract: When a label name is selected, a plurality of prompt associated with the selected label name are displayed one after the other on a display so that a user can easily know what text data needs to be inputted. The text memory stores text data inputted as prompted by each of the plurality of prompts associated with the selected label name. Also the text memory retrieves, from a registration layout information memory, print layout information for printing the inputted text data. The print mechanism prints the text data stored in the text memory on a tape based on the print layout information. In this way, a label printed with the text data, that can be adhered to the binding of files and the like, can be produced quickly and easily.

Abstract: A document processing device which includes an input device for inputting characters, symbols and various instructions; a display having a cursor; a text memory for storing input data, such as the characters and symbols; a print element for printing the input data stored in the text memory; and a controller for controlling the input device, the display and the print element also includes the ability to set a fixed format mode in order to print the input data in a fixed format; a non-volatile fixed format information memory containing prescribed preset fixed formats such that the input data input in the fixed format mode is stored; a format information memory which is provided in the text memory and serves to store format information to print the input data, and an ability to read in the fixed format information from the fixed format information memory and transmit it to the format information memory.

Abstract: An apparatus and method of printing characters and symbols either vertically or horizontally on an elongated recording medium adjusts the position of vertically printed characters and symbols so that the vertically printed characters and symbols are evenly spaced on the recording medium. When a vertical printing is to be accomplished, dot pattern data in a data development buffer is rotated 90 degrees counterclockwise, and transferred to a vertical data development buffer. The rotated dot pattern data for each character is then moved in the longitudinal direction of the recording medium, as necessary, to ensure that each character will be positioned in the middle of its character pitch. The longitudinal adjustment ensures that the upper and the lower margin of each character are equal.

Abstract: In a synchronous DRAM required to be capable of performing high-speed consecutive operations in synchronism with a clock signal, a DBI-line pair is connected between a DQ-line pair and an RDB-line pair, and pipeline operation whose single cycle time is divided into four periods is employed.

Abstract: In a driver circuit for driving a pair of data lines, the amplitude of a differential input signal is reduced from 2.5 V to 0.6 V, which is smaller than a conventional lower-limit source voltage (approximately 1.5 V). The amplitude of the differential signal transmitted through the pair of data lines is amplified to 2.5 V by an amplifying circuit and the resulting signal is then latched by a latch circuit. After the latching by the latch circuit, the operation of the amplifying circuit is halted. The driver circuit is constituted solely by a plurality of NMOS transistors so as not to increase a leakage current flowing in the off state. Here, the threshold voltage of the NMOS transistor positioned on the ground side is reduced to a conventional lower-limit value (0.3 V to 0.6 V), while the threshold voltage of the NMOS transistor on the power-source side to a value lower than the above lower-limit value (0 V to 0.3 V), thereby enhancing a driving force of the NMOS transistor on the power-source side.

Abstract: N-piece redundant address comparing circuits are individually composed of impedance converting circuits, so that information using redundancy is transmitted as an impedance value. Consequently, even though the N becomes larger as the capacity of a memory becomes larger, a signal line having large capacitance and the node of a redundant judging circuit are not charged or discharged. A high-speed operation can be realized without being affected by the capacitance of the signal line or by the capacitance of the node of the redundant judging circuit.

Abstract: A tape print device for printing bar codes on a print tape includes: an input unit for inputting data indicative of a bar code desired to be printed on a tape; a data storage unit for temporarily storing the inputted data; an increment unit for serially incrementing at least a part of the data stored in the data storage means at least one time, in accordance with a predetermined order, to thereby produce at least one incremented data indicative of at least one incremented bar code, the thus produced at least one incremented data being stored in the data storage means; a print data generating unit for producing print data for the desired bar code and the at least one incremented bar code, based on the data stored in the data storage means; and a printing unit for receiving the print data and for printing images of the desired bar code and the at least one incremented bar code on a print tape.

Abstract: A character string and data characters for printing a bar code are first input, and a print key is operated. When the data read from a text memory of the apparatus are character data, the apparatus creates dot pattern data for printing the character string as per the character size selected. When bar code starting data are read, the data following the characters are read out and converted into bar code data. After the data representing a left-hand side margin of the bar code are generated, dot pattern data constituting the bar code are created in accordance with the height of the character size selected. Then, a right-hand side margin of the bar code is generated.

Abstract: A tape printing apparatus having a test printing function for printing a predetermined test pattern onto a tape upon operation of an appropriate key includes a printing part, a tape width detector, a memory and a print control unit. The printing part prints the predetermined test pattern. The tape width detector detects the width of the currently loaded tape. The memory stores test pattern data by which to print any one of a plurality of different test patterns depending on the tape width detected by the tape width detector. The print control unit retrieves from the memory the test pattern data corresponding to the detected tape width upon operation of the appropriate key and causes the printing part to print the test pattern onto the tape based on the retrieved test pattern data. Because the tape printing apparatus prints the test pattern according to the width of the currently loaded tape, an operator can determine what printing is available for that particular tape.

Abstract: An external power supply voltage V.sub.CC is applied to a peripheral circuit as a first internal power supply voltage V.sub.PERI. A power supply voltage control circuit outputs a voltage control signal V.sub.SIG of a high logic level if V.sub.CC is not greater than a low limit voltage V.sub.0L in a voltage range specified by VCC recommended operating conditions, otherwise it outputs V.sub.SIG of a low logic level. A power supply circuit applies a second internal power supply voltage V.sub.W and a third internal power supply voltage V.sub.WORD to a memory cell section. V.sub.W is equal to V.sub.PERI if V.sub.SIG is HIGH, while on the other hand V.sub.W is a voltage as a result of boosting V.sub.PERI. V.sub.WORD is a voltage as a result of boosting VW to a further extent. A row decoder sends out V.sub.W onto an enable signal line of a row of sense amplifiers, and V.sub.WORD onto a word line of a memory cell array so that V.sub.W becomes a high-logic-level data write voltage to a memory cell.

Abstract: In a semiconductor memory having a redundant circuit, a plurality of first normal cells and a plurality of first spare cells are connected to a first pair of data lines, and a plurality of second normal cells and a plurality of second spare cells are connected to a second pair of data lines. Both pairs of data lines are connected to an output data line through a selecting amplifier. A normal cell is selected based on a combination of NGWL1, NGWL2, . . . with BLK1, BLK2, both NGWL1, NGWL2, . . . and BLK1, BLK2 being supplied from a decoder, and a spare cell is selected based on a combination of the BLK1, BLK2 supplied from the decoder with SGWL1, SGWL2, . . . supplied from a redundancy judging circuit. A second spare cell is selected when a first normal cell is selected, and a first spare cell is selected when a second normal cell is selected. Only at the time when a spare address is entered, one of the SGWL1, SGWL 2, . . . is raised.