Abstract: A resin composition and a multilayer body that includes the resin composition layer, the resin composition being characterized by containing a propylene-based polymer (A) in the range of 5 to 70% by weight; a soft propylene-based polymer (B) in the range of 30 to 95% by weight; a propylene-based polymer (C) graft-modified with an ethylenically unsaturated monomer, in the range of 0.1 to 20% by weight; a polyethylene (D) in the range of 0 to 20% by weight; and an ethylene/?-olefin random copolymer (E) in the range of 1 to 30% by weight, provided that a total amount of (A), (B), (C), (D), and (E) is 100% by weight.

Abstract: A lubricating oil composition with a resin (A) and a base oil (B), the resin (A) is in a range of 0.01 to 50 parts by mass per 100 parts of (A) and (B), the resin (A) satisfies the following requirements: (A-1) the resin (A) is a polymer including a constituent unit from 4-methyl-1-pentene in a range of 60 to 99 mol % and a constituent unit from an ?-olefin having 2 to 20 carbon atoms (excluding 4-methyl-1-pentene) in a range of 1 to 40 mol % (provided that 4-methyl-1-pentene and the ?-olefin is 100 mol %); (A-2) intrinsic viscosity [?] measured in decalin at 135° C. is in a range of 0.01 to 5.0 dl/g; (A-3) a melting point (Tm) is in a range of 110 to 150° C. as determined by DSC; and the base oil (B) has (B-1) kinematic viscosity at 100° C. is in a range of 1 to 50 mm2/s.

Abstract: A lubricating oil composition includes an ethylene/?-olefin copolymer (A) having 70 to 90 mole % of structural units derived from ethylene and an intrinsic viscosity [?] of 0.3 to 1.0 dl/g.

Abstract: A bias adjustment device uses an identification model developed by machine learning using training data, and includes a calculation unit that calculates first identification accuracy of the identification model trained on first training data and second identification accuracy of the identification model trained on second training data acquired by an adjustment of the number of pieces of data of the first training data, a prediction unit that predicts a change in identification accuracy with respect to the number of pieces of training data on the basis of the first identification accuracy and the second identification accuracy, and a control unit that adjusts the number of pieces of data used for the training or changes the identification model, on the basis of the predicted change in the identification accuracy, in such a manner that the predicted change in the identification accuracy becomes a predetermined target value.

Abstract: A lubricating oil composition with a resin (A) and a base oil (B), the resin (A) is in a range of 0.01 to 50 parts by mass per 100 parts of (A) and (B), the resin (A) satisfies the following requirements: (A-1) the resin (A) is a polymer including a constituent unit from 4-methyl-1-pentene in a range of 60 to 99 mol % and a constituent unit from an ?-olefin having 2 to 20 carbon atoms (excluding 4-methyl-1-pentene) in a range of 1 to 40 mol % (provided that 4-methyl-1-pentene and the ?-olefin is 100 mol %); (A-2) intrinsic viscosity [?] measured in decalin at 135° C. is in a range of 0.01 to 5.0 dl/g; (A-3) a melting point (Tm) is in a range of 110 to 150° C. as determined by DSC; and the base oil (B) has (B-1) kinematic viscosity at 100° C. is in a range of 1 to 50 mm2/s.

Abstract: An object of the present invention is to provide a lubricating oil composition particularly excellent in viscosity characteristics at a low temperature. The present invention provides: a lubricating oil composition including a polymer (A) and a base oil (B), wherein the polymer (A) satisfies the following requirement (A-1), and the content ratio of the polymer (A) and the base oil (B) is such that the ratio of a resin (A) is within the range of from 0.1 to 50 parts by mass with respect to 100 parts by mass of the total amount of the polymer (A) and the base oil (B). (A-1) The polymer (A) is a polymer containing a structural unit derived from an ?-olefin having 20 or less carbon atoms.

Abstract: A lubricating oil composition includes an ethylene/?-olefin copolymer (A) having 70 to 90 mole % of structural units derived from ethylene and an intrinsic viscosity [?] of 0.3 to 1.0 dl/g.

Abstract: An object of the present invention is to provide a lubricating oil composition particularly excellent in viscosity characteristics at a low temperature. The present invention provides: a lubricating oil composition including a polymer (A) and a base oil (B), wherein the polymer (A) satisfies the following requirement (A-1), and the content ratio of the polymer (A) and the base oil (B) is such that the ratio of a resin (A) is within the range of from 0.1 to 50 parts by mass with respect to 100 parts by mass of the total amount of the polymer (A) and the base oil (B). (A-1) The polymer (A) is a polymer containing a structural unit derived from an ?-olefin having 20 or less carbon atoms.

Abstract: A viscosity modifier for lubricating oils according to the present invention contains a resin (?), wherein the resin (?) satisfies specific requirements, and contains a grafted olefin polymer [R1] which is composed of a main chain and a side chain(s) and which satisfies the following requirements (i) and (ii). (i) The main chain is composed of a copolymer of ethylene and at least one ?-olefin selected from ?-olefins having from 3 to 12 carbon atoms, and contains the structural units derived from ethylene within the range of from 74 to 86 mol %. (ii) The side chain(s) is/are composed of a copolymer of ethylene and at least one ?-olefin selected from ?-olefins having from 3 to 12 carbon atoms, and contain(s) the structural units derived from ethylene within the range of from 30 to 65 mol %.

Abstract: A single-chip microcomputer comprising: a first bus having a central processing unit and a cache memory connected therewith; a second bus having a dynamic memory access control circuit and an external bus interface connected therewith; a break controller for connecting the first bus and the second bus selectively; a third bus having a peripheral module connected therewith and having a lower-speed bus cycle than the bus cycles of the first and second buses; and a bus state controller for effecting a data transfer and a synchronization between the second bus and the third bus. The single-chip microcomputer has the three divided internal buses to reduce the load capacity upon the signal transmission paths so that the signal transmission can be accomplished at a high speed. Moreover, the peripheral module required to have no operation speed is isolated so that the power dissipation can be reduced.

Abstract: A single-chip microcomputer comprising: a first bus having a central processing unit and a cache memory connected therewith; a second bus having a dynamic memory access control circuit and an external bus interface connected therewith; a break controller for connecting the first bus and the second bus selectively; a third bus having a peripheral module connected therewith and having a lower-speed bus cycle than the bus cycles of the first and second buses; and a bus state controller for effecting a data transfer and a synchronization between the second bus and the third bus. The single-chip microcomputer has the three divided internal buses to reduce the load capacity upon the signal transmission paths so that the signal transmission can be accomplished at a high speed. Moreover, the peripheral module required to have no operation speed is isolated so that the power dissipation can be reduced.

Abstract: A single-chip microcomputer comprising: a first bus having a central processing unit and a cache memory connected therewith; a second bus having a dynamic memory access control circuit and an external bus interface connected therewith; a break controller for connecting the first bus and the second bus selectively; a third bus having a peripheral module connected therewith and having a lower-speed bus cycle than the bus cycles of the first and second buses; and a bus state controller for effecting a data transfer and a synchronization between the second bus and the third bus. The single-chip microcomputer has the three divided internal buses to reduce the load capacity upon the signal transmission paths so that the signal transmission can be accomplished at a high speed. Moreover, the peripheral module required to have no operation speed is isolated so that the power dissipation can be reduced.

Abstract: A single-chip microcomputer comprising: a first bus having a central processing unit and a cache memory connected therewith; a second bus having a dynamic memory access control circuit and an external bus interface connected therewith; a break controller for connecting the first bus and the second bus selectively; a third bus having a peripheral module connected therewith and having a lower-speed bus cycle than the bus cycles of the first and second buses; and a bus state controller for effecting a data transfer and a synchronization between the second bus and the third bus. The single-chip microcomputer has the three divided internal buses to reduce the load capacity upon the signal transmission paths so that the signal transmission can be accomplished at a high speed. Moreover, the peripheral module required to have no operation speed is isolated so that the power dissipation can be reduced.

Abstract: A single-chip microcomputer comprising: a first bus having a central processing unit and a cache memory connected therewith; a second bus having a dynamic memory access control circuit and an external bus interface connected therewith; a break controller for connecting the first bus and the second bus selectively; a third bus having a peripheral module connected therewith and having a lower-speed bus cycle than the bus cycles of the first and second buses; and a bus state controller for effecting a data transfer and a synchronization between the second bus and the third bus. The single-chip microcomputer has the three divided internal buses to reduce the load capacity upon the signal transmission paths so that the signal transmission can be accomplished at a high speed. Moreover, the peripheral module required to have no operation speed is isolated so that the power dissipation can be reduced.

Abstract: A single-chip microcomputer comprising: a first bus having a central processing unit and a cache memory connected therewith; a second bus having a dynamic memory access control circuit and an external bus interface connected therewith; a break controller for connecting the first bus and the second bus selectively; a third bus having a peripheral module connected therewith and having a lower-speed bus cycle than the bus cycles of the first and second buses; and a bus state controller for effecting a data transfer and a synchronization between the second bus and the third bus. The single-chip microcomputer has the three divided internal buses to reduce the load capacity upon the signal transmission paths so that the signal transmission can be accomplished at a high speed. Moreover, the peripheral module required to have no operation speed is isolated so that the power dissipation can be reduced.

Abstract: A single-chip microcomputer comprising: a first bus having a central processing unit and a cache memory connected therewith; a second bus having a dynamic memory access control circuit and an external bus interface connected therewith; a break controller for connecting the first bus and the second bus selectively; a third bus having a peripheral module connected therewith and having a lower-speed bus cycle than the bus cycles of the first and second buses; and a bus state controller for effecting a data transfer and a synchronization between the second bus and the third bus. The single-chip microcomputer has the three divided internal buses to reduce the load capacity upon the signal transmission paths so that the signal transmission can be accomplished at a high speed. Moreover, the peripheral module required to have no operation speed is isolated so that the power dissipation can be reduced.

Abstract: A single-chip microcomputer comprising: a first bus having a central processing unit and a cache memory connected therewith; a second bus having a dynamic memory access control circuit and an external bus interface connected therewith; a break controller for connecting the first bus and the second bus selectively; a third bus having a peripheral module connected therewith and having a lower-speed bus cycle than the bus cycles of the first and second buses; and a bus state controller for effecting a data transfer and a synchronization between the second bus and the third bus. The single-chip microcomputer has the three divided internal buses to reduce the load capacity upon the signal transmission paths so that the signal transmission can be accomplished at a high speed. Moreover, the peripheral module required to have no operation speed is isolated so that the power dissipation can be reduced.

Abstract: A single-chip microcomputer comprising: a first bus having a central processing unit and a cache memory connected therewith; a second bus having a dynamic memory access control circuit and an external bus interface connected therewith; a break controller for connecting the first bus and the second bus selectively; a third bus having a peripheral module connected therewith and having a lower-speed bus cycle than the bus cycles of the first and second buses; and a bus state controller for effecting a data transfer and a synchronization between the second bus and the third bus. The single-chip microcomputer has the three divided internal buses to reduce the load capacity upon the signal transmission paths so that the signal transmission can be accomplished at a high speed. Moreover, the peripheral module required to have no operation speed is isolated so that the power dissipation can be reduced.

Abstract: A single-chip microcomputer comprising: a first bus having a central processing unit and a cache memory connected therewith; a second bus having a dynamic memory access control circuit and an external bus interface connected therewith; a break controller for connecting the first bus and the second bus selectively; a third bus having a peripheral module connected therewith and having a lower-speed bus cycle than the bus cycles of the first and second buses; and a bus state controller for effecting a data transfer and a synchronization between the second bus and the third bus. The single-chip microcomputer has the three divided internal buses to reduce the load capacity upon the signal transmission paths so that the signal transmission can be accomplished at a high speed. Moreover, the peripheral module required to have no operation speed is isolated so that the power dissipation can be reduced.

Abstract: A single-chip microcomputer comprising: a first bus having a central processing unit and a cache memory connected therewith; a second bus having a dynamic memory access control circuit and an external bus interface connected therewith; a break controller for connecting the first bus and the second bus selectively; a third bus having a peripheral module connected therewith and having a lower-speed bus cycle than the bus cycles of the first and second buses; and a bus state controller for effecting a data transfer and a synchronization between the second bus and the third bus. The single-chip microcomputer has the three divided internal buses to reduce the load capacity upon the signal transmission paths so that the signal transmission can be accomplished at a high speed. Moreover, the peripheral module required to have no operation speed is isolated so that the power dissipation can be reduced.