Patents by Inventor Akio Hayakawa

Akio Hayakawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Single-chip microcomputer operable in master and slave modes and having configurable bus control terminals
    Patent number: 6212620
    Abstract: A single-chip microcomputer comprising: a first bus having a central processing unit and a cache memory connected therewith; a second bus having a dynamic memory access control circuit and an external bus interface connected therewith; a break controller for connecting the first bus and the second bus selectively; a third bus having a peripheral module connected therewith and having a lower-speed bus cycle than the bus cycles of the first and second buses; and a bus state controller for effecting a data transfer and a synchronization between the second bus and the third bus. The single-chip microcomputer has the three divided internal buses to reduce the load capacity upon the signal transmission paths so that the signal transmission can be accomplished at a high speed. Moreover, the peripheral module required to have no operation speed is isolated so that the power dissipation can be reduced.
    Type: Grant
    Filed: November 13, 1998
    Date of Patent: April 3, 2001
    Assignee: Hitachi, Ltd.
    Inventors: Shumpei Kawasaki, Yasushi Akao, Kouki Noguchi, Atsushi Hasegawa, Hiroshi Ohsuga, Keiichi Kurakazu, Kiyoshi Matsubara, Akio Hayakawa, Yoshitaka Ito
  • Microcomputer having multiple bus structure coupling CPU to other processing elements
    Patent number: 5930523
    Abstract: A single-chip microcomputer comprising: a first bus having a central processing unit and a cache memory connected therewith; a second bus having a dynamic memory access control circuit and an external bus interface connected therewith; a break controller for connecting the first bus and the second bus selectively; a third bus having a peripheral module connected therewith and having a lower-speed bus cycle than the bus cycles of the first and second buses; and a bus state controller for effecting a data transfer and a synchronization between the second bus and the third bus. The single-chip microcomputer has the three divided internal buses to reduce the load capacity upon the signal transmission paths so that the signal transmission can be accomplished at a high speed. Moreover, the peripheral module required to have no operation speed is isolated so that the power dissipation can be reduced.
    Type: Grant
    Filed: April 3, 1998
    Date of Patent: July 27, 1999
    Assignees: Hitachi Ltd., Hitachi ULSI Engineering Corp.
    Inventors: Shumpei Kawasaki, Yasushi Akao, Kouki Noguchi, Atsushi Hasegawa, Hiroshi Ohsuga, Keiichi Kurakazu, Kiyoshi Matsubara, Akio Hayakawa, Yoshitaka Ito