Abstract: In a method and apparatus for designing semiconductor integrated circuit, a path delay information producing section produces path delay information by performing a static timing analysis based on delay information of a cell and subject circuit information. A correction table producing section calculates circuit-dependent delay variation for each combination of circuit parameter values based on variation information of an element, and stores the calculated circuit-dependent delay variation in a delay correction table. A statistical path delay producing section calculates the circuit parameters for a path based on the subject circuit information and the path delay information, obtains the corresponding circuit-dependent delay variation based on the circuit-dependent delay variation correction table, and calculates and outputs statistical path delay information based on the circuit-dependent delay variation and the corresponding path delay information.

Abstract: A scan flip-flop circuit including an input section employing a dynamic circuit and an output section employing a static circuit, capable of latching in data within a period of a pulse width that is shorter than the clock cycle, wherein only three N-type transistors are connected in series in the input section employing a dynamic circuit. A data signal is input directly to one of the three N-type transistors. On the other hand, a test input signal is input to an AND/OR inverter circuit. The AND/OR inverter circuit receives, as a control signal, the potential of the node obtained as the clock signal passes through two inverter circuits. Therefore, there is required only a short hold time for the test input signal.

Abstract: There is provided a flip flop circuit with a scan structure which is formed by an input section of a dynamic circuit and an output section of a static circuit wherein data is taken in within an interval of a short pulse width as compared with a clock cycle. In the dynamic circuit of the input section, the number of serially-connected MOS transistors to which a data signal is input is smaller than the number of serially-connected MOS transistors to which a test input signal is input. With this structure, the speed of operation is increased at the time of data storage for a data signal input, and the number of MOS transistors is reduced.

Abstract: In a level shifter, in the case where the amplitude voltage of an input signal (i.e., a first power voltage VDDL) input to an input terminal is changed to be higher and the amplitude voltage of an output signal (i.e., a second power voltage VDDH) output from an output terminal is changed to be lower, a fall delay time of the signal output from the output terminal tends to be longer than a rise delay time of the signal. However, an inverted input signal obtained by an inverter is input to a level shifting unit and also to the gate of an N-type transistor, and therefore, the N-type transistor is turned on at the fall of the input signal input to the input terminal, so as to supply a current based on the second power voltage VDDH to an output node of the level shifting unit for assisting the shift into H level performed in the level shifting unit.

Abstract: The clock supply circuit of the present invention comprises a plurality of clock supply paths and a clock gate circuit. The clock supply paths branch a clock signal and supply each of the branched clock signals to a plurality of sequential circuits via a buffer. The clock gate circuit is inserted at least to one of the clock supply paths, which lets through the clock signals when a control signal is in a first logic state and, when the control signal is in a second logic state, outputs an inversion signal of a logic level that is outputted in a previous occasion where the control signal in the second logic state is applied.

Abstract: In a level shifter, in the case where the amplitude voltage of an input signal (i.e., a first power voltage VDDL) input to an input terminal is changed to be higher and the amplitude voltage of an output signal (i.e., a second power voltage VDDH) output from an output terminal is changed to be lower, a fall delay time of the signal output from the output terminal tends to be longer than a rise delay time of the signal. However, an inverted input signal obtained by an inverter is input to a level shifting unit and also to the gate of an N-type transistor, and therefore, the N-type transistor is turned on at the fall of the input signal input to the input terminal, so as to supply a current based on the second power voltage VDDH to an output node of the level shifting unit for assisting the shift into H level performed in the level shifting unit.

Abstract: A dummy MOSFET including a dummy gate separates nMOSFETs included in adjacent memory cells arranged in the direction in which bit lines extend. This configuration reduces a stress applied from an STI to the channel regions of the nMOSFETs. Accordingly, decrease of drive currents of the nMOSFETs is suppressed.

Abstract: There is provided a flip flop circuit with a scan structure which is formed by an input section of a dynamic circuit and an output section of a static circuit wherein data is taken in within an interval of a short pulse width as compared with a clock cycle. In the dynamic circuit of the input section, the number of serially-connected MOS transistors to which a data signal is input is smaller than the number of serially-connected MOS transistors to which a test input signal is input. With this structure, the speed of operation is increased at the time of data storage for a data signal input, and the number of MOS transistors is reduced.

Abstract: In a flip-flop circuit which includes an input section using a dynamic circuit and an output section using a static circuit and which captures data during a period of a pulse width shorter than a clock cycle, the number of transistors, circuit area and power consumption are reduced. In FIG. 1, an output signal of an inverter circuit INV1 constituting a latch circuit 2 connected to the output terminal of an input section 1 is used as an input signal of a control section 3. Thus, a control signal output from the control section 3 to the input section 1 is stabilized, thereby suppressing unnecessary operation of circuit elements and reducing unnecessary power consumption. In addition, the configuration of the control section 3 is simplified. As a result, the number of transistors constituting the circuit and the circuit area can be reduced.

Abstract: A dummy MOSFET including a dummy gate separates nMOSFETs included in adjacent memory cells arranged in the direction in which bit lines extend. This configuration reduces a stress applied from an STI to the channel regions of the nMOSFETs. Accordingly, decrease of drive currents of the nMOSFETs is suppressed.

Abstract: In a level shifter, in the case where the amplitude voltage of an input signal (i.e., a first power voltage VDDL) input to an input terminal is changed to be higher and the amplitude voltage of an output signal (i.e., a second power voltage VDDH) output from an output terminal is changed to be lower, a fall delay time of the signal output from the output terminal tends to be longer than a rise delay time of the signal. However, an inverted input signal obtained by an inverter is input to a level shifting unit and also to the gate of an N-type transistor, and therefore, the N-type transistor is turned on at the fall of the input signal input to the input terminal, so as to supply a current based on the second power voltage VDDH to an output node of the level shifting unit for assisting the shift into H level performed in the level shifting unit.

Abstract: In a flip-flop circuit which includes an input section using a dynamic circuit and an output section using a static circuit and which captures data during a period of a pulse width shorter than a clock cycle, the number of transistors, circuit area and power consumption are reduced.

Abstract: A multiple inverter system of the present invention is disclosed. It includes a plurality of input transformers having secondary windings and a plurality of unit inverter cells connected in series at n stages to compose respective phases and supply the electric power to a multiple phase load in combination with the input transformers. The input transformers have 3n sets of three-phase windings at the secondary side and the secondary windings of the transformers, which are out-of-phase at each phase, are connected to unit inverter cells of each phase at the n-th stages. Further, the present invention is provided with a bypass switch control to melt a fuse that is applicable to a unit inverter given with a circuit closing command by giving this circuit closing command to a bypass switch corresponding to applicable unit inverters in response to an operation abnormality detector and a DC abnormality detector.

Abstract: A power converter having at least a pair of voltage drive switching elements, which comprises a gate control circuit, the gate control circuit comprising a detecting section for detecting at least one of a set of device parameters and a set of electric parameters of the voltage drive switching elements, a monitoring section for monitoring at least one of states of turn-on and turn-off of the voltage drive switching elements based on the at least one of a set of device parameters and a set of electric parameters of the voltage drive switching elements detected by the detecting section, and a control section for controlling a gate of the voltage drive switching elements based on a monitoring result of the monitoring section.

Abstract: A power inverting method and system for connecting a plurality of AC power supplies to a common bus line in parallel wherein the AC power supplies are independently controlled so that power supplies with different rating characteristics can be coupled to the common bus line without adverse effects such as the existence of cross currents flowing between the different power supplies. In each AC power supply there is provided a system parameter calculating unit for calculating optimum load current, system impedance and output voltage parameters of the power supply which are then output to a reference data producing unit which generates appropriate feedback voltage and phase signals for output to a voltage controller and a phase synchronization controller, respectively. The voltage controller and phase synchronization controller output feedback signals to a power inverter which varies the power supply output.

Abstract: A power supply is energized by an external power source and a battery, and supplies electric power to a load. The power supply includes a battery voltage detector and a current detector for detecting a discharge current from the battery. The remaining capacity of the battery is detected in accordance with a change in the battery voltage when the external power source is free of power failure. The battery voltage change is defined as the difference between an initial voltage of the battery and an active voltage of the battery obtained when the battery is discharged by the detected discharge current for a predetermined period of time.

Abstract: A turbine helper drive apparatus includes a turbine for driving a load, a motor coupled to the turbine, and a power converter for controlling an output from the motor based on a predetermined power reference. The power converter controls the motor so that the motor performs either a motoring operation, wherein the motor drives the load together with the turbine, or a regenerating operation, wherein the motor serves as a load for the turbine to generate an electric power.

Abstract: A helper drive apparatus for a turbine drive system in which a load is mainly driven by a turbine and a helper motor is used for assisting the drive for the load, comprising: a turbine control circuit, coupled to the turbine, for controlling output power of the turbine in accordance with a turbine power reference signal; a motor control circuit, coupled to the helper motor, for controlling output power of the helper motor in accordance with a motor power reference signal; a speed control means, coupled to the turbine, for detecting a difference between a given speed reference signal and a speed signal indicating an operation speed of the turbine, and providing a master power reference signal representing the difference; and a power sharing ratio control circuit, coupled to the speed control circuit, turbine control circuit, and motor control circuit, and being responsive to a given power sharing instruction signal, for sharing the master power reference signal to the turbine power reference signal and the mot

Abstract: A self-extinguishing element such as a gate turn-off thyristor (GTO) is used for each arm of the inverter. A capacitive load is connected to the output terminal of the inverter. In a region where the output frequency of the inverter is low, the self-extinguishing element is forcibly commutated. In a high-frequency region, where the output frequency of the inverter is higher than that in the low-frequency region, the capacitive load causes the self-extinguishing element to be load-commutated.

Abstract: A turbine helper drive apparatus has an induction motor coupled to a turbine, and a power converter for power-controlling the motor. Part of the load of the turbine is shared by the motor in accordance with preset power for power control, so that auxiliary drive to compensate for the insufficient capacity of the turbine is performed and cheaper, late-night electric power is effectively utilized.