Abstract: According to the present invention, a secret key cryptosystem and tamper-proof hardware are used to realize a pseudo-public key cryptosystem at a low cost. A trap-door one-way function is substantially realized with the use of tamper-proof hardware. Each user performs communication using equipment provided with hardware having the same capabilities described below. Such hardware retains association between an ID and a key. In response to a request from a user, the hardware issues and stores an ID, and it can perform decryption and generation of a MAC (message authentication code) with a key associated with the ID. A user publishes his ID. When performing encryption, a message sender encrypts a message using the published ID. A third person can perform decryption with the ID only by analyzing the mechanism in the hardware. However, the hardware has a capability of destroying itself when such an act is attempted.

Abstract: An image drawing system, an image drawing server, an image drawing method, and a computer program product that provides a three-dimensional world to a client-terminal. The method includes: providing a viewpoint in the vicinity of an avatar and creating a three-dimensional object; performing a perspective projection of a static object to create a two-dimensional panoramic image; overlaying the two-dimensional panoramic image, information on a dynamic object, and an image of the avatar; and storing the two-dimensional panoramic image. The computer program product tangibly embodies instructions which when implemented causes a computer to execute the steps of the method. The system includes: a three-dimensional object creation unit; a panoramic image creation unit; a drawing unit for overlaying; and a panoramic image storage unit. The server includes: a reception unit; a three-dimensional object creation unit; a panoramic image creation unit; and a transmission unit.

Abstract: A personal service support method for assisting an inquiry about a user operation in a virtual world, a computer program product, and a system for the same. The method includes: storing a dialog between a user and an agent; connecting the dialog in a list structure with another dialog in the list structure to produce a created dialog in a branch tree structure; and recording the created dialog in the branch tree structure. The computer program product tangibly embodies instructions which when implemented causes a computer to execute the steps of the method. The system includes: a dialog storage unit which stores a dialog between a user and an agent; and a dialog creating unit which connects the dialog in the list structure with another dialog in the list structure to create a dialog in a branch tree structure.

Abstract: A compiler optimizing conversion of a character coding system for a character stored in a string variable in a target program to be optimized has a conversion instruction generation section which generates a conversion instruction to convert a character from a first character coding system to a second character coding system and to store the converted character in the string variable, the conversion instruction being generated before each of a plurality of procedures by which the character in the string variable written in the first character coding system is read out and is used in the second character coding system, and a conversion instruction removal section which removes each of conversion instructions generated by the conversion instruction generation section if a character in the second character coding system is stored in the string variable in each of the execution paths executed before the conversion instruction.

Abstract: Enhances program efficiency by performing optimization with reduced influence of an explicit instruction for adjusting an image of local variables of a code column executed by means of an interpreter and a compiled code column. An example embodiment, includes: setting code that is ignorable in predetermined transformation for a second code column among codes in a first code column, which affects transformation of the second code column; and performing predetermined transformation for the second code column by ignoring the code that is set to be ignorable, when an execution object of a program transitions from a first code column executed by means of an interpreter to a second compiled code column. It can further include generating a compensating code required for transforming a second code column including propagation of a copy instruction, and inserting the code into a first code column prior to transformation of the second code column.

Abstract: A system of the present invention includes: a memory device which includes a first memory area for storing first information indicating that a first task acquires or attempts to acquire a lock, and a second memory area for storing second information indicating that a second task acquires or attempts to acquire the lock, and in which a time lag may occur between a time when the first task issues a writing instruction and a time when the written content is enabled to be referred to by the second task; a first acquisition section which reads the second memory area after issuing a writing instruction to write the first information to the first memory area in response to a request from the first task, and which makes a reply indicating a success of the lock acquisition on condition that the second information is not read; and a second acquisition section which writes the second information to the second memory area in response to a request from the second task, which enables the written content to be referred to b

Abstract: A system including a memory device that stores, in association with each of a plurality of areas obtained by dividing an input image, an feature amount of an object drawn in the area; a selection section that selects a range of the input image to be recognized by a user based on an instruction therefrom; a calculation section that reads the feature amount corresponding to each area contained in the selected range from the memory device, and calculates an index value based on each read feature amount; and a control section that controls a device which acts on an acoustic sense or a touch sense based on the calculated index value.

Abstract: An XML parser for inputting XML event strings which constitute an XML document to be processed, and an XPath evaluating unit for executing evaluation of the XPath by streaming processing are provided. This XPath evaluating unit serially evaluates the XPath with respect to the respective XML events transferred from the XML parser, and retains information concerning a result of partial evaluation of this XPath when the XPath is partially established for a given XML event. Then, when the last step of this XPath is established, the XPath is judged as established for the XML document.

Abstract: A method for processing a multidimensional array object in which a multidimensional array is implemented by an array of array objects. The multidimensional array object comprises array objects which constitute the multidimensional array. Flags representing that it is possible to optimize a process for elements of the multidimensional array object are added as additional information. The flags are stored in a storage device (main memory for instance). Then, a machine code corresponding to a state of the flags is executed.

Abstract: In order to improve the efficiency of execution of a program by prefetching data necessary to execute the program, a system is provided that causes a computer to execute a recursive query prior to a program being subjected to prefetching. This system detects from iterative processing in the program a query to generate a resultant table by selecting a record that satisfies a selection condition from a target table. The system generates an initial query to generate an initial table that includes values of variables that are set prior to starting the iterative processing in the program.

Abstract: In a multiprocessor computer system, a lock operation is maintained with a thread using non-atomic instructions. Identifiers are assigned to each thread. Flags in conjunction with the thread identifiers are used to determine the continuity of the lock with a thread. However, in the event continuity of the lock with the thread ceases, a compare-and-swap operation is executed to reset the lock with the same thread or another thread. Similarly, in the event there has been a collision between two or more threads requesting the lock, a compare-and-swap operation is executed to assign the lock to one of the requesting threads. Accordingly, prolonged ownership of a lock operation by a thread is encouraged to mitigate use of atomic operations in granting of the lock to a non-owning thread.

Abstract: A computer for a service provider receives from each member of two groups who is a user of a service via a mediating computer, a priority list in which member IDs of the other group is permuted in the priority order of a user and processing information that are encrypted so as not to be decrypted by the mediating computer. The ID of the priority list is encrypted with an encrypting key that is common to all members. The computer for a service provider performs matching, with ID in the priority list being left encrypted when the list is decrypted. The computer for a service provider decrypts the processing information, makes it in a state in which the matching result can be decrypted based on the processing information by only a person concerned, and sends it to each member via the mediating computer.

Abstract: An exclusion controller which allows an information processing unit to acquire a contended resource to the exclusion of the other information processing units includes a plurality of non-prioritized information processing units mutually exclusively acquiring a non-prioritized exclusion right, which indicates a candidate for acquiring the contended resource, by a first process. The exclusion controller further includes a prioritized information processing unit acquiring the contended resource by a second process, which requires a shorter processing time than the first process, to the exclusion of the non-prioritized information processing unit having acquired the non-prioritized exclusion right.

Abstract: An exclusion controller which allows an information processing unit to acquire a contended resource to the exclusion of the other information processing units includes a plurality of non-prioritized information processing units mutually exclusively acquiring a non-prioritized exclusion right, which indicates a candidate for acquiring the contended resource, by a first process. The exclusion controller further includes a prioritized information processing unit acquiring the contended resource by a second process, which requires a shorter processing time than the first process, to the exclusion of the non-prioritized information processing unit having acquired the non-prioritized exclusion right.

Abstract: A compiler includes a register allocator for allocating registers for instructions in a program to be compiled, and a code generator for generating object code based on the register allocation results performed by the register allocator. The register allocator allocates logical registers for instructions in the program to be compiled. The register allocation further allocates, to physical registers, the logical registers that are allocated to the instructions of the program, so that the physical registers that are live at a procedure call in the program to be compiled are allocated from the bottom of the register stack.

Abstract: Assigns suitable registers to a plurality of variables. A compiler converts a source program into instructions for a processor having: a simultaneously used variable acquisition section which obtains, with respect to each of a plurality of variables used in the source program, some of the other variables used simultaneously with the variable; an allocation sequence generation section which generates a plurality of allocation sequences between the plurality of variables to allocate each variable to one of the plurality of registers different from those to which some of the other variables used simultaneously with the variable are allocated; an allocation priority acquisition section which obtains allocation priorities indicating to which one of the plurality of registers each variable is allocated with priority; and a register allocation section which allocates the variables to registers in accordance with an allocation sequence selected on the basis of the allocation priorities.

Abstract: A system of the present invention includes: a memory device which includes a first memory area for storing first information indicating that a first task acquires or attempts to acquire a lock, and a second memory area for storing second information indicating that a second task acquires or attempts to acquire the lock, and in which a time lag may occur between a time when the first task issues a writing instruction and a time when the written content is enabled to be referred to by the second task; a first acquisition section which reads the second memory area after issuing a writing instruction to write the first information to the first memory area in response to a request from the first task, and which makes a reply indicating a success of the lock acquisition on condition that the second information is not read; and a second acquisition section which writes the second information to the second memory area in response to a request from the second task, which enables the written content to be referred to b

Abstract: A compiler includes a register allocator for allocating registers for instructions in a program to be compiled, and a code generator for generating object code based on the register allocation results performed by the register allocator. The register allocator allocates logical registers for instructions in the program to be compiled. The register allocation further allocates, to physical registers, the logical registers that are allocated to the instructions of the program, so that the physical registers that are live at a procedure call in the program to be compiled are allocated from the bottom of the register stack.

Abstract: A compiler includes a register allocator for allocating registers for instructions in a program to be compiled, and a code generator for generating object code based on the register allocation results performed by the register allocator. The register allocator allocates logical registers for instructions in the program to be compiled, register allocation further allocates, to physical registers, the logical registers that are allocated to the instructions of the program, so that the physical registers that are live at a procedure call in the program to be compiled are allocated from the bottom of the register stack.

Abstract: A computer for a service provider receives from each member of two groups who is a user of a service via a mediating computer, a priority list in which member IDs of the other group is permuted in the priority order of a user and processing information that are encrypted so as not to be decrypted by the mediating computer. The ID of the priority list is encrypted with an encrypting key that is common to all members. The computer for a service provider performs matching, with ID in the priority list being left encrypted when the list is decrypted. The computer for a service provider decrypts the processing information, makes it in a state in which the matching result can be decrypted based on the processing information by only a person concerned, and sends it to each member via the mediating computer.