Abstract: Assigns suitable registers to a plurality of variables. A compiler converts a source program into instructions for a processor having: a simultaneously used variable acquisition section which obtains, with respect to each of a plurality of variables used in the source program, some of the other variables used simultaneously with the variable; an allocation sequence generation section which generates a plurality of allocation sequences between the plurality of variables to allocate each variable to one of the plurality of registers different from those to which some of the other variables used simultaneously with the variable are allocated; an allocation priority acquisition section which obtains allocation priorities indicating to which one of the plurality of registers each variable is allocated with priority; and a register allocation section which allocates the variables to registers in accordance with an allocation sequence selected on the basis of the allocation priorities.

Abstract: A method and system are provided for efficiently retrieving an entity bean in an EJB Container. The retrieval of beans is divided into multiple pieces of processing, and each retrieval is executed by an independent thread. There is one main thread and a plurality of auxiliary threads. Each of the auxiliary threads processes data obtained by a prior processing thread based upon a speculative primary key and places the processed data in a queue of a next thread. One of the threads is assigned to store the processed data in associative memory. The main thread uses an actual primary key in conjunction with the data placed in the associative memory to process data. Accordingly, speculative creation of bean instances is performed with independent multiple threads.

Abstract: According to the present invention, a secret key cryptosystem and tamper-proof hardware are used to realize a pseudo public key cryptosystem at a low cost. A trap-door one-way function is substantially realized with the use of tamper-proof hardware. Each user performs communication using equipment provided with hardware having the same capabilities described below. Such hardware retains association between an ID and a key. In response to a request from a user, the hardware issues and stores an ID, and it can perform decryption and generation of a MAC (message authentication code) with a key associated with the ID. A user publishes his ID. When performing encryption, a message sender encrypts a message using the published ID. A third person can perform decryption with the ID only by analyzing the mechanism in the hardware. However, the hardware has a capability of destroying itself when such an act is attempted.

Abstract: In order to improve the efficiency of execution of a program by prefetching data necessary to execute the program, a system is provided that causes a computer to execute a recursive query prior to a program being subjected to prefetching. This system detects from iterative processing in the program a query to generate a resultant table by selecting a record that satisfies a selection condition from a target table. The system generates an initial query to generate an initial table that includes values of variables that are set prior to starting the iterative processing in the program.

Abstract: A method and system are provided to automatically generating structured query language (SQL) to accelerate program execution in a database. Analysis of a target program checks usage status of objects and field data, and to determine which columns and table of a database record are required for program access. The SQL is generated to return only necessary data based upon which columns of which tables of the database record are likely to be accessed by the program.

Abstract: To save and restore the contents of registers efficiently and enhance the execution efficiency of compilation. For a predetermined variable in an executable program, a determination is made whether or not the variable lives across invoking of a predetermined function, and if so, the kind of invoking of the function is determined. The variable is allocated to any of volatile registers, non-volatile registers, and semi-volatile registers, based on this determination. Also, it is determined to which register the variable living across invoking of the function is allocated, based on an execution frequency of the function when the executable program is run.

Abstract: A system to controls access to a database, including: an acquiring section which acquires an access program including a plurality of database access instructions; a detecting section which detects a plurality of different tables in the database that are accessed by the plurality of access instructions; a join control section which executes a join instruction prior to the execution of the access instructions, the join instruction obtaining a result table from the database by combining the plurality of different tables detected; and a conversion control section which executes a conversion instruction prior to the execution of the plurality of access instructions, the conversion instruction extracting records from the result table for the access instructions and converting the records into the form of a structure accessible for the plurality of access instructions.

Abstract: A master content generation unit generates information (master content) that is concretized based on the original idea of a content generator. An intermediate content generation unit re-constructs a complete and concrete content that has an adequate amount of information at a lower level, and generates a content to be sold. When a purchaser (a buyer) issues a request for a desired level, such as for the amount of information, to the intermediate content generation unit via the new content requesting unit, the content is re-constructed in accordance with the request. A content retailing unit provides a price for the master content and the content that is generated by the intermediate content generation unit, and collects the requested purchase price from a buyer. The buyer may select content equivalent to the compensation that corresponds to the buyer's request, and may purchase it from the content retaining unit.

Abstract: A computer, computer compiler and method for reducing the number of interferences between variables during graph coloring while maintaining the possibility that the instructions will be executed in parallel. A compiler, which converts into a machine language the source code of a program written in a programming language and optimizes the program includes: a directed acyclic graph DAG analysis unit 11 for constructing and analyzing a DAG for an instruction in a program to be processed; an interference graph construction unit 12 for employing the analysis results to construct an interference graph representing the probability that an interference will occur between variables used by the instructions; and a graph coloring unit 13 for allocating registers for the instruction based on the interference graph that is constructed.

Abstract: In a multiprocessor computer system, a lock operation is maintained with a thread using non-atomic instructions. Identifiers are assigned to each thread. Flags in conjunction with the thread identifiers are used to determine the continuity of the lock with a thread. However, in the event continuity of the lock with the thread ceases, a compare-and-swap operation is executed to reset the lock with the same thread or another thread. Similarly, in the event there has been a collision between two or more threads requesting the lock, a compare-and-swap operation is executed to assign the lock to one of the requesting threads. Accordingly, prolonged ownership of a lock operation by a thread is encouraged to mitigate use of atomic operations in granting of the lock to a non-owning thread.

Abstract: A method for processing a multidimensional array object in which a multidimensional array is implemented by an array of array objects. The multidimensional array object comprises array objects which constitute the multidimensional array. Flags representing that it is possible to optimize a process for elements of the multidimensional array object are added as additional information. The flags are stored in a storage device (main memory for instance). Then, a machine code corresponding to a state of the flags is executed.

Abstract: Provides a compiler which optimizes conversion of a character coding system for a character stored in a string variable in a target program to be optimized has a conversion instruction generation section which generates a conversion instruction to convert a character from a first character coding system to a second character coding system and to store the converted character in the string variable before each of a plurality of procedures by which the character in the string variable written in the first character coding system is read out and is used in the second character coding system, and a conversion instruction removal section which removes each of conversion instructions generated by the conversion instruction generation section if a character in the second character coding system is stored in the string variable in each of the execution paths executed before the conversion instruction.

Abstract: A compiler is provided which effectively performs a data flow optimization process for a program wherein a plurality of branches and merges are arranged in series, without incurring a drastic increase in the amount of code. The compiler, and the method thereof, may be implemented in hardware, software, or both.

Abstract: A method for processing a multidimensional array object in which a multidimensional array is implemented by an array of array objects. The multidimensional array object comprises array objects which constitute the multidimensional array. Flags representing that it is possible to optimize a process for elements of the multidimensional array object are added as additional information. The flags are stored in a storage device (main memory for instance). Then, a machine code corresponding to a state of the flags is executed.

Abstract: Compiler for optimizing a load instruction in a program, including: executable range detecting means for detecting executable range of load instruction in execution paths tracing back execution procedures from a target load, where the range can hold data read by the load instruction into register and transmit data to execution position of target load instruction when load instruction is executed; instruction generating means for generating a precedent load instruction, executed prior to target load instruction in executable range, within the executable range for each of the execution paths when the precedent load instruction for reading the same data from the same address as the target load instruction is absent; and instruction replacing means for deleting the target load instruction and replacing an instruction using the data read by the target load instruction with an instruction using data which are read by the precedent load instruction.

Abstract: An XML parser for inputting XML event strings which constitute an XML document to be processed, and an XPath evaluating unit for executing evaluation of the XPath by streaming processing are provided. This XPath evaluating unit serially evaluates the XPath with respect to the respective XML events transferred from the XML parser, and retains information concerning a result of partial evaluation of this XPath when the XPath is partially established for a given XML event. Then, when the last step of this XPath is established, the XPath is judged as established for the XML document.

Abstract: An exclusion controller which allows an information processing unit to acquire a contended resource to the exclusion of the other information processing units includes a plurality of non-prioritized information processing units mutually exclusively acquiring a non-prioritized exclusion right, which indicates a candidate for acquiring the contended resource, by a first process. The exclusion controller further includes a prioritized information processing unit acquiring the contended resource by a second process, which requires a shorter processing time than the first process, to the exclusion of the non-prioritized information processing unit having acquired the non-prioritized exclusion right.

Abstract: Enhances program efficiency by performing optimization with reduced influence of an explicit instruction for adjusting an image of local variables of a code column executed by means of an interpreter and a compiled code column. An example embodiment, includes: setting code that is ignorable in predetermined transformation for a second code column among codes in a first code column, which affects transformation of the second code column; and performing predetermined transformation for the second code column by ignoring the code that is set to be ignorable, when an execution object of a program transitions from a first code column executed by means of an interpreter to a second compiled code column. It can further include generating a compensating code required for transforming a second code column including propagation of a copy instruction, and inserting the code into a first code column prior to transformation of the second code column.

Abstract: A compiler includes a register allocator for allocating registers for instructions in a program to be compiled, and a code generator for generating object code based on the register allocation results performed by the register allocator. The register allocator allocates logical registers for instructions in the program to be compiled. Register allocation further allocates, to physical registers, the logical registers that are allocated to the instructions of the program, so that the physical registers that are live at a procedure call in the program to be compiled are allocated from the bottom of the register stack.

Abstract: Assigns suitable registers to a plurality of variables. A compiler converts a source program into instructions for a processor having: a simultaneously used variable acquisition section which obtains, with respect to each of a plurality of variables used in the source program, some of the other variables used simultaneously with the variable; an allocation sequence generation section which generates a plurality of allocation sequences between the plurality of variables to allocate each variable to one of the plurality of registers different from those to which some of the other variables used simultaneously with the variable are allocated; an allocation priority acquisition section which obtains allocation priorities indicating to which one of the plurality of registers each variable is allocated with priority; and a register allocation section which allocates the variables to registers in accordance with an allocation sequence selected on the basis of the allocation priorities.