Abstract: A semiconductor inspecting method according to an embodiment includes a step of scanning a semiconductor device with laser light to acquire characteristic information indicative of characteristics of an electrical signal of the semiconductor device in response to irradiation with the laser light for each of irradiation positions of the laser light and to generate a first pattern image of the semiconductor device based on characteristic information for each of irradiation positions, a step of generating a second pattern image of the semiconductor device based on a layout image of the semiconductor device and current path information indicative of a current path in the semiconductor device, and a step of acquiring matching information indicative of a relative relationship between the first pattern image and the layout image based on a result of positional alignment between the first pattern image and the second pattern image.

Abstract: A semiconductor inspection device includes: a measuring device that supplies power to a semiconductor device and measures the electrical characteristics of the semiconductor device; an optical scanning device that scans the semiconductor device with light intensity-modulated with a plurality of frequencies; a lock-in amplifier that acquires a characteristic signal indicating the electrical characteristics of the plurality of frequency components; and an inspection device that corrects a phase component of the characteristic signal at an arbitrary scanning position with a phase component at a scanning position reflecting the electrical characteristics of a first layer in the semiconductor device as a reference, specifies a phase component of the characteristic signal at a scanning position reflecting the electrical characteristics of a second layer, normalizes the phase component of the characteristic signal at the arbitrary scanning position by using the phase component, and outputs a result based on the norm

Abstract: A semiconductor inspection device includes: a measuring device that supplies power to a semiconductor device and measures the electrical characteristics; an optical scanning device that scans the semiconductor device with light intensity-modulated with a plurality of frequencies; a lock-in amplifier that acquires a characteristic signal indicating the electrical characteristics of the plurality of frequency components; and an inspection device that calculates a frequency at which the characteristic signal reflecting the electrical characteristics of a first layer and the characteristic signal reflecting the electrical characteristics of a second layer have a predetermined phase difference, corrects a phase component of the characteristic signal at an arbitrary scanning position with a phase component at the scanning position reflecting the electrical characteristics of the first layer as a reference, and outputs an in-phase component and a quadrature component at the arbitrary scanning position at the calcula

Abstract: An inspection apparatus includes a light sensor that detects light from a semiconductor device to which an electric signal has been input, an optical system that guides light from the semiconductor device to the light sensor, and a control device electrically connected to the light sensor. The control device includes a measurement unit that acquires waveform data obtained by optical measurement for each of a plurality of positions on a defective semiconductor device and waveform data obtained by the optical measurement for each of a plurality of positions on a non-defective semiconductor device, a calculation unit that calculates a degree of correspondence between the waveform data of the defective semiconductor device and the waveform data of the non-defective semiconductor device, and an analysis unit that analyzes a defective part of the defective semiconductor device on the basis of the degree of correspondence for each of the plurality of positions.

Abstract: A failure analysis unit is a wafer conveyance unit configured to convey a wafer while holding the wafer in a semiconductor failure analysis apparatus, the wafer conveyance unit including: a placement table configured to fix a wafer at a predetermined observation position; and a wafer chuck configured to convey the wafer while holding the wafer to the observation position. The wafer chuck includes a plurality of holding members (protruding portions) provided so as to face a side surface of the wafer, and holds the wafer by sandwiching a peripheral portion of the wafer W with the plurality of holding members.

Abstract: An inspection apparatus includes a light sensor that detects light from a semiconductor device to which an electric signal has been input, an optical system that guides light from the semiconductor device to the light sensor, and a control device electrically connected to the light sensor. The control device includes a measurement unit that acquires waveform data obtained by optical measurement for each of a plurality of positions on a defective semiconductor device and waveform data obtained by the optical measurement for each of a plurality of positions on a non-defective semiconductor device, a calculation unit that calculates a degree of correspondence between the waveform data of the defective semiconductor device and the waveform data of the non-defective semiconductor device, and an analysis unit that analyzes a defective part of the defective semiconductor device on the basis of the degree of correspondence for each of the plurality of positions.

Abstract: A semiconductor device inspection apparatus includes: a light sensor that detects light from a semiconductor device as a DUT to which an electric signal has been input; an optical system that guides light from the semiconductor device to the light sensor; and a control device electrically connected to the light sensor. The control device includes: a data reading unit that reads mask data indicating a mask layout of the semiconductor device; a search unit that searches for a position of a transistor in the semiconductor device on the basis of polygon data of a gate layer of the semiconductor device included in the mask data; a setting unit that sets the searched position of the transistor as an optical measurement target position; and a measurement unit that performs optical measurement for the set optical measurement target position to acquire a measurement result.

Abstract: A semiconductor device inspection apparatus is an apparatus for inspecting a semiconductor device which is an object to be inspected based on a result signal which is output in accordance with input of a test pattern signal to the semiconductor device, the apparatus including: an ultrasonic transducer, disposed to face the semiconductor device, which generates ultrasonic waves; a stage for moving a relative position of the semiconductor device and the ultrasonic transducer; a stimulation condition control unit for controlling a condition of stimulation by the ultrasonic waves applied to the semiconductor device; and an analysis unit for generating a measurement image based on the result signal which is output from the semiconductor device.

Abstract: An inspection method according to an embodiment is an inspection method of performing laser marking on a semiconductor device (D) including a substrate (SiE) and a metal layer (ME) formed on the substrate (SiE), and the inspection method includes specifying a fault point (fp) in the semiconductor device (D) by inspecting the semiconductor device (D), and irradiating the semiconductor device (D) with laser light having a wavelength that is transmitted through the substrate (SiE) from the substrate (SiE) side so that a marking is formed at least at a boundary between the substrate (SiE) and the metal layer (ME) on the basis of the fault point (fp).

Abstract: A semiconductor device inspection apparatus includes: a light sensor that detects light from a semiconductor device as a DUT to which an electric signal has been input; an optical system that guides light from the semiconductor device to the light sensor; and a control device electrically connected to the light sensor. The control device includes: a data reading unit that reads mask data indicating a mask layout of the semiconductor device; a search unit that searches for a position of a transistor in the semiconductor device on the basis of polygon data of a gate layer of the semiconductor device included in the mask data; a setting unit that sets the searched position of the transistor as an optical measurement target position; and a measurement unit that performs optical measurement for the set optical measurement target position to acquire a measurement result.

Abstract: An inspection method according to an embodiment is an inspection method of performing laser marking on a semiconductor device (D) including a substrate (SiE) and a metal layer (ME) formed on the substrate (SiE), and the inspection method includes specifying a fault point (fp) in the semiconductor device (D) by inspecting the semiconductor device (D), and irradiating the semiconductor device (D) with laser light having a wavelength that is transmitted through the substrate (SiE) from the substrate (SiE) side so that a marking is formed at least at a boundary between the substrate (SiE) and the metal layer (ME) on the basis of the fault point (fp).

Abstract: An inspection method according to an embodiment is an inspection method of performing laser marking on a semiconductor device including a substrate and a metal layer formed on the substrate, and the inspection method includes specifying a fault point in the semiconductor device by inspecting the semiconductor device, and irradiating the semiconductor device with laser light having a wavelength that is transmitted through the substrate from the substrate side so that a marking is formed at least at a boundary between the substrate and the metal layer on the basis of the fault point.

Abstract: An inspection method according to an embodiment is an inspection method of performing laser marking on a semiconductor device including a substrate and a metal layer formed on the substrate, and the inspection method includes specifying a fault point in the semiconductor device by inspecting the semiconductor device, and irradiating the semiconductor device with laser light having a wavelength that is transmitted through the substrate from the substrate side so that a marking is formed at least at a boundary between the substrate and the metal layer on the basis of the fault point.

Abstract: A semiconductor device inspection apparatus is an apparatus for inspecting a semiconductor device which is an object to be inspected based on a result signal which is output in accordance with input of a test pattern signal to the semiconductor device, the apparatus including: an ultrasonic transducer, disposed to face the semiconductor device, which generates ultrasonic waves; a stage for moving a relative position of the semiconductor device and the ultrasonic transducer; a stimulation condition control unit for controlling a condition of stimulation by the ultrasonic waves applied to the semiconductor device; and an analysis unit for generating a measurement image based on the result signal which is output from the semiconductor device.

Abstract: A failure analysis apparatus 10 is composed of an inspection information acquirer 11 for acquiring a failure observed image P2 of a semiconductor device, a layout information acquirer 12 for acquiring layout information, and a failure analyzer 13 for analyzing a failure. The failure analyzer 13 extracts as a candidate interconnection for a failure, an interconnection passing an analysis region, out of a plurality of interconnections, using interconnection information to describe a configuration of interconnections in the semiconductor device by a pattern data group of interconnection patterns in respective layers, and, for extracting the candidate interconnection, it performs an equipotential trace of the interconnection patterns using the pattern data group, thereby extracting the candidate interconnection.

Abstract: A failure analysis apparatus 10 is composed of an inspection information acquirer 11 for acquiring a failure observed image P2 of a semiconductor device, a layout information acquirer 12 for acquiring layout information, and a failure analyzer 13 for analyzing a failure. The failure analyzer 13 extracts candidate nets passing at least one of analysis regions set from the failure observed image, out of a plurality of nets in the semiconductor device, and passage counts of the respective candidate nets through the analysis regions, selects a candidate net with the largest passage count as a first failure net, and selects a second failure net with attention to analysis regions where the first failure net does not pass. This substantializes a semiconductor failure analysis apparatus, failure analysis method, and failure analysis program capable of securely and efficiently performing the analysis of the failure of the semiconductor device using the failure observed image.

Abstract: Electrical testing is to be performed on a semiconductor integrated circuit device which the test pads formed. To facilitate such testing, the method of manufacture of the semiconductor integrated circuit device employs a probe card which has two or more contact terminals which can contact two or more electrodes. This probe card includes, in opposition to a wiring substrate of the semiconductor integrated circuit device in which a first wiring is formed, a first sheet having two or more contact terminals to contact the two or more electrodes; a second wiring electrically connected to the two or more contact terminals and the first wiring; and first dummy wirings which are near the region of formation of the two or more contact terminals, are arranged to a non-forming region of the second wiring, and do not participate in signal transfer.

Abstract: A failure analysis apparatus 10 is composed of an inspection information acquirer 11 for acquiring a failure observed image P2 of a semiconductor device, a layout information acquirer 12 for acquiring layout information, and a failure analyzer 13 for analyzing a failure. The failure analyzer 13 extracts as a candidate interconnection for a failure, an interconnection passing an analysis region, out of a plurality of interconnections, using interconnection information to describe a configuration of interconnections in the semiconductor device by a pattern data group of interconnection patterns in respective layers, and, for extracting the candidate interconnection, it performs an equipotential trace of the interconnection patterns using the pattern data group, thereby extracting the candidate interconnection.

Abstract: A failure analysis apparatus 10 is composed of an inspection information acquirer 11 for acquiring a failure observed image P2 of a semiconductor device, a layout information acquirer 12 for acquiring layout information, and a failure analyzer 13 for analyzing a failure of the semiconductor device. The failure analyzer 13 has an analysis region setter for comparing an intensity distribution in the failure observed image with a predetermined intensity threshold to extract a reaction region arising from a failure, and for setting an analysis region used in the failure analysis of the semiconductor device, in correspondence to the reaction region. This substantializes a semiconductor failure analysis apparatus, failure analysis method, and failure analysis program capable of securely and efficiently performing the analysis of the failure of the semiconductor device using the failure observed image.

Abstract: A failure analysis apparatus 10 is composed of an inspection information acquirer 11 for acquiring a failure observed image P2 of a semiconductor device, a layout information acquirer 12 for acquiring layout information, and a failure analyzer 13 for analyzing a failure. The failure analyzer 13 extracts candidate nets passing at least one of analysis regions set from the failure observed image, out of a plurality of nets in the semiconductor device, and passage counts of the respective candidate nets through the analysis regions, selects a candidate net with the largest passage count as a first failure net, and selects a second failure net with attention to analysis regions where the first failure net does not pass. This substantializes a semiconductor failure analysis apparatus, failure analysis method, and failure analysis program capable of securely and efficiently performing the analysis of the failure of the semiconductor device using the failure observed image.