Patents by Inventor Akira Shimase

Akira Shimase has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7301146
    Abstract: A probe driving method and a probe apparatus for bringing a probe into contact with the surface of a sample in a safe and efficient manner by monitoring the probe height. Information about the height of the probe from the sample surface is obtained by detecting a probe shadow (54) appearing immediately before the probe contacts the sample, or based on a change in relative positions of a probe image and a sample image that are formed as an ion beam is irradiated diagonally.
    Type: Grant
    Filed: August 11, 2005
    Date of Patent: November 27, 2007
    Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.
    Inventors: Satoshi Tomimatsu, Hidemi Koike, Junzo Azuma, Tohru Ishitani, Aritoshi Sugimoto, Yuichi Hamamura, Isamu Sekihara, Akira Shimase
  • Patent number: 7271015
    Abstract: Electrical testing is to be performed on a semiconductor integrated circuit device which the test pads formed. To facilitate such testing, the method of manufacture of the semiconductor integrated circuit device employs a probe card which has two or more contact terminals which can contact two or more electrodes. This probe card includes, in opposition to a wiring substrate of the semiconductor integrated circuit device in which a first wiring is formed, a first sheet having two or more contact terminals to contact the two or more electrodes; a second wiring electrically connected to the two or more contact terminals and the first wiring; and first dummy wirings which are near the region of formation of the two or more contact terminals, are arranged to a non-forming region of the second wiring, and do not participate in signal transfer.
    Type: Grant
    Filed: April 7, 2005
    Date of Patent: September 18, 2007
    Assignee: Renesas Technology Corp.
    Inventors: Masayoshi Okamoto, Hideyuki Matsumoto, Shingo Yorisaki, Akio Hasebe, Yasuhiro Motoyama, Akira Shimase
  • Publication number: 20070190671
    Abstract: Electrical testing is to be performed on a semiconductor integrated circuit device which the test pads formed. To facilitate such testing, the method of manufacture of the semiconductor integrated circuit device employs a probe card which has two or more contact terminals which can contact two or more electrodes. This probe card includes, in opposition to a wiring substrate of the semiconductor integrated circuit device in which a first wiring is formed, a first sheet having two or more contact terminals to contact the two or more electrodes; a second wiring electrically connected to the two or more contact terminals and the first wiring; and first dummy wirings which are near the region of formation of the two or more contact terminals, are arranged to a non-forming region of the second wiring, and do not participate in signal transfer.
    Type: Application
    Filed: April 12, 2007
    Publication date: August 16, 2007
    Inventors: Masayoshi Okamoto, Hideyuki Matsumoto, Shingo Yorisaki, Akio Hasebe, Yasuhiro Motoyama, Akira Shimase
  • Publication number: 20070020781
    Abstract: A failure analysis apparatus 10 is composed of an inspection information acquirer 11 for acquiring a failure observed image P2 of a semiconductor device, a layout information acquirer 12 for acquiring layout information, a failure analyzer 13 for analyzing a failure of the semiconductor device, and an analysis screen display controller 14 for letting a display device 40 display information about a result of the analysis. The failure analyzer 13 sets an analysis region with reference to the failure observed image P2, and extracts a net passing the analysis region, from a plurality of nets included in a layout of the semiconductor device. This substantializes a semiconductor failure analysis apparatus, analysis method, and analysis program capable of securely and efficiently performing the analysis of the failure of the semiconductor device.
    Type: Application
    Filed: April 24, 2006
    Publication date: January 25, 2007
    Inventors: Toshiyuki Majima, Akira Shimase, Hirotoshi Terada, Kazuhiro Hotta, Masahiro Takeda
  • Publication number: 20050269511
    Abstract: A probe driving method and a probe apparatus for bringing a probe into contact with the surface of a sample in a safe and efficient manner by monitoring the probe height. Information about the height of the probe from the sample surface is obtained by detecting a probe shadow (54) appearing immediately before the probe contacts the sample, or based on a change in relative positions of a probe image and a sample image that are formed as an ion beam is irradiated diagonally.
    Type: Application
    Filed: August 11, 2005
    Publication date: December 8, 2005
    Inventors: Satoshi Tomimatsu, Hidemi Koike, Junzo Azuma, Tohru Ishitani, Aritoshi Sugimoto, Yuichi Hamamura, Isamu Sekihara, Akira Shimase
  • Patent number: 6960765
    Abstract: A probe driving method and a probe apparatus for bringing a probe into contact with the surface of a sample in a safe and efficient manner by monitoring the probe height. Information about the height of the probe from the sample surface is obtained by detecting a probe shadow appearing immediately before the probe contacts the sample, or based on a change in relative positions of a probe image and a sample image that are formed as an ion beam is irradiated diagonally.
    Type: Grant
    Filed: June 8, 2001
    Date of Patent: November 1, 2005
    Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.
    Inventors: Satoshi Tomimatsu, Hidemi Koike, Junzo Azuma, Tohru Ishitani, Aritoshi Sugimoto, Yuichi Hamamura, Isamu Sekihara, Akira Shimase
  • Publication number: 20050227383
    Abstract: Electrical testing is to be performed on a semiconductor integrated circuit device which the test pads formed. To facilitate such testing, the method of manufacture of the semiconductor integrated circuit device employs a probe card which has two or more contact terminals which can contact two or more electrodes. This probe card includes in opposition to a wiring substrate of the semiconductor integrated circuit device in which a first wiring is formed, a first sheet having two or more contact terminals to contact the two or more electrodes; a second wiring electrically connected to the two or more contact terminals and the first wiring; and first dummy wirings which are near the region of formation of the two or more contact terminals, are arranged to a non-forming region of the second wiring, and do not participate in signal transfer.
    Type: Application
    Filed: April 7, 2005
    Publication date: October 13, 2005
    Inventors: Masayoshi Okamoto, Hideyuki Matsumoto, Shingo Yorisaki, Akio Hasebe, Yasuhiro Motoyama, Akira Shimase
  • Patent number: 6753253
    Abstract: Herein disclosed are a variety of techniques relating to the wiring and logic corrections on a chip by making use of the focused ion beam (which is shortly referred to as “FIB”) or the laser selection metal CVD. The time periods for the wiring corrections and for debugging and developing an electronic system are shortened by making use of the processing characteristics of the FIB. Illustratively, a hole is bored in an insulating film above a portion of a wiring which is to be connected to another wiring by means of a focused ion beam. The inside of the hole and a predetermined region on the insulating film are irradiated with either a laser beam or an ion beam in a metal compound gas to deposit metal in the hole and on said region and a connecting wiring is formed by means of optically pumped CVD.
    Type: Grant
    Filed: September 18, 1990
    Date of Patent: June 22, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Takahiko Takahashi, Fumikazu Itoh, Akira Shimase, Mikio Hongo, Satoshi Haraichi, Hiroshi Yamaguchi
  • Publication number: 20030184332
    Abstract: A probe driving method and a probe apparatus for bringing a probe into contact with the surface of a sample in a safe and efficient manner by monitoring the probe height. Information about the height of the probe from the sample surface is obtained by detecting a probe shadow (54) appearing immediately before the probe contacts the sample, or based on a change in relative positions of a probe image and a sample image that are formed as an ion beam is irradiated diagonally.
    Type: Application
    Filed: November 29, 2002
    Publication date: October 2, 2003
    Inventors: Satoshi Tomimatsu, Hidemi Koike, Junzo Azuma, Tohru Ishitani, Aritoshi Sugimoto, Yuichi Hamamura, Isamu Sekihara, Akira Shimase
  • Patent number: 6507029
    Abstract: In an electron particle machine for observing, inspecting, processing or analyzing a semiconductor wafer as a substrate or a sample, a light source is installed in a preparation chamber. A chucking stage for chucking the semiconductor wafer with a chuck using static electricity is provided with parts for connecting to earth such that they are in contact with the chucked semiconductor wafer. After the chuck using static electricity is released after observation, inspection, process or analysis, a surface of the semiconductor wafer and the parts for connecting to earth are irradiated with light from the light source. This provides conductivity to the surface of the semiconductor wafer, so that charge accumulated on the semiconductor wafer is removed from the surface through the parts for connecting to earth.
    Type: Grant
    Filed: February 23, 1999
    Date of Patent: January 14, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Norimasa Nishimura, Akira Shimase, Junzou Azuma, Asahiro Kuni, Hiroya Koshishiba
  • Patent number: 6476387
    Abstract: In a method for observing or processing and analyzing the surface of a sample by irradiating a charged beam on the sample covered at least partially by an insulator film, an ultraviolet light is irradiated possibly as pulse on the sample (substrate), thereby transforming the insulator into a conductive material due to the photoconductivity effect, thereby transforming the surface of the sample (substrate) into a conductive material, so that charged particles are grounded from a grounded portion in order to prevent the charged beam from being repulsed due to charged particles of the irradiated charged beam accumulated in the insulator formed on the surface of the sample (substrate).
    Type: Grant
    Filed: May 14, 1999
    Date of Patent: November 5, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Norimasa Nishimura, Akira Shimase, Junzou Azuma, Yuichi Hamamura, Michinobu Mizumura, Yasuhiro Koizumi, Hidemi Koike
  • Patent number: 6465781
    Abstract: A method and an apparatus for inspecting or measuring a sample based on charged-particle beam are provided to relieve charge-up of the sample, so that high-quality electron image is obtained. A UV light irradiation optical system is controlled by an irradiation controller, scanning of the charged-particle beam is controlled by a scanning controller, and the irradiation controller and the scanning controller are controlled by a general controller. They are mutually synchronized, and a signal from an electron detector is imaged by an image slicing circuit and an image processing circuit.
    Type: Grant
    Filed: June 8, 2000
    Date of Patent: October 15, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Norimasa Nishimura, Akira Shimase, Masahiro Watanabe, Asahiro Kuni, Taku Ninomiya, Hiroshi Miyai
  • Patent number: 6344115
    Abstract: A pattern forming method using an improved charged particle beam process, and a charged particle beam processing system prevent effectively the corrosion of a workpiece by a reactive gas adsorbed by and adhering to the surface of the workpiece when the workpiece is taken out into the atmosphere after pattern formation. The charged particle beam processing system comprises, as principal components, an ion beam chamber provided with an ion beam optical system, a processing chamber provided with a gas nozzle through which a reactive gas is blown against a workpiece, a load-lock chamber connected through a gate valve to the processing chamber. The load-lock chamber is capable of producing a plasma of an inert gas for processing the surface of the workpiece by sputtering.
    Type: Grant
    Filed: October 13, 1999
    Date of Patent: February 5, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Junzou Azuma, Akira Shimase, Yuichi Hamamura, Hidemi Koike
  • Patent number: 6303932
    Abstract: A secondary charged particle image acquisition method and its apparatus for detecting a secondary charged particle image. The method includes the steps of irradiating a surface of a specimen with a focused charged particle beam and detecting a secondary charged particle emanated from the surface of the specimen, obtaining a secondary charged particle image based on the detected secondary charged particle, irradiating a positive ion beam on the surface of the specimen where the focused charged particle beam is irradiated and inducing a conductive layer on the surface of the specimen by the irradiation of the positive ion beam and diffusing an electric charge on the surface of the conductive layer.
    Type: Grant
    Filed: November 19, 1998
    Date of Patent: October 16, 2001
    Assignee: Hitachi, Ltd.
    Inventors: Yuichi Hamamura, Akira Shimase, Junzou Azuma, Michinobu Mizumura, Norimasa Nishimura, Yasuhiro Koizumi, Hidemi Koike
  • Patent number: 5976328
    Abstract: A pattern forming method using an improved charged particle beam process, and a charged particle beam processing system prevent effectively the corrosion of a workpiece by a reactive gas adsorbed by and adhering to the surface of the workpiece when the workpiece is taken out into the atmosphere after pattern formation. The charged particle beam processing system comprises, as principal components, an ion beam chamber provided with an ion beam optical system, a processing chamber (18) provided with a gas nozzle through which a reactive gas is blown against a workpiece, a load-lock chamber connected through a gate valve to the processing chamber. The load-lock chamber is capable of producing a plasma of an inert gas for processing the surface of the workpiece by sputtering.
    Type: Grant
    Filed: January 27, 1997
    Date of Patent: November 2, 1999
    Assignee: Hitachi, Ltd.
    Inventors: Junzou Azuma, Akira Shimase, Yuichi Hamamura, Hidemi Koike
  • Patent number: 5952658
    Abstract: A charged particle beam milling system which is designed in such a way that a milling end point is judged to stop the milling on the basis of a change in the magnitude of secondary ion signals generated when milling an electronic device such as an LSI having a multi-wiring layer structure, in which a wiring layer and an insulating layer are laminated, using a charged particle beam.
    Type: Grant
    Filed: April 18, 1997
    Date of Patent: September 14, 1999
    Assignee: Hitachi, Ltd.
    Inventors: Akira Shimase, Yuichi Hamamura, Junzou Azuma, Michinobu Mizumura
  • Patent number: 5825035
    Abstract: A processing method using a plasma ion source for generating a focused ion beam, characterized by covering, with an insulator, an inner wall of a plasma holding vessel excluding a reference electrode for applying a voltage to a plasma and an ion extraction electrode for extracting ions from the plasma, and employing means of continuously controlling the absolute value of an ion beam current in a range of from 1 to 10 .mu.A by changing the absolute value of an ion extraction voltage applied between the reference electrode and the ion extraction electrode in a range of from 0 to 100 V; and an apparatus for carrying out the processing method. This is advantageous in stabilizing the ion beam current and in preventing the ion beam from being made dim even when the current value of the ion beam is changed.
    Type: Grant
    Filed: November 8, 1996
    Date of Patent: October 20, 1998
    Assignee: Hitachi, Ltd.
    Inventors: Michinobu Mizumura, Yuuichi Hamamura, Junzou Azuma, Akira Shimase, Takashi Kamimura, Fumikazu Itoh, Kaoru Umemura, Yoshimi Kawanami, Yuuichi Madokoro
  • Patent number: 5824598
    Abstract: An IC wiring connecting method for interconnecting conductive lines of the same wiring plane of an IC chip for correcting the wiring, for interconnecting conductive lines of different wiring lanes of a multilayer IC chip at the same position, or for connecting a conductive line of a lower wiring plane of a multilayer IC chip to a conductive line formed at a separate position on the same multilayer IC chip. The insulating film or films covering conductive lines to be interconnected are processed by an energy beam such as a concentrated ion beam to form holes so as to expose the respective parts of the conductive lines where the conductive lines are to be interconnected, then a metal is deposited over the surfaces of the holes and an area interconnecting the holes by irradiating the surfaces of the holes and the area by an energy beam or a concentrated ion beam in an atmosphere of a gaseous organic metal compound to form a conductive metal film electrically interconnecting the conductive lines.
    Type: Grant
    Filed: November 21, 1995
    Date of Patent: October 20, 1998
    Assignee: Hitachi, Ltd.
    Inventors: Hiroshi Yamaguchi, Mikio Hongo, Tateoki Miyauchi, Akira Shimase, Satoshi Haraichi, Takahiko Takahashi, Keiya Saito
  • Patent number: 5683547
    Abstract: A processing method and apparatus using a focused energy beam for conducting local energy beam processing in a focused energy beam irradiating area by irradiating a sample with a focused energy beam such as an ion beam or an electron beam in an etching gas atmosphere. As the etching gas, a mixed gas different in composition from any conventional one is employed and the gas is uniformly supplied to an etching area and at least one of the components of such a mixed gas is a spontaneous reactive gas for use in etching the sample spontaneously and isotropically. With this arrangement, it is possible to subject to local etching a material for which the local etching has been impossible to provide since a single etching gas causes a reaction too fierce or causes almost nearly no reaction.
    Type: Grant
    Filed: July 12, 1994
    Date of Patent: November 4, 1997
    Assignee: Hitachi, Ltd.
    Inventors: Junzou Azuma, Fumikazu Itoh, Satoshi Haraichi, Akira Shimase, Junichi Mori, Takahiko Takahashi, Emiko Uda
  • Patent number: 5656811
    Abstract: A method for making a specimen for use in observation through a transparent electron microscope, includes a step of milling part of the specimen into a thin film part, which can be observed through a transparent electron microscope, by scanning and irradiating a focused ion beam onto the specimen, a step of observing a mark for detection of a position provided on the specimen as a secondary charged particle image by scanning and irradiating a charged particle beam onto the specimen without irradiating the charged particle beam onto the portion to be milled into the thin film part during the milling, and a step of compensating for positional drift of the focused ion beam during milling in accordance with a result of the observation.
    Type: Grant
    Filed: June 14, 1995
    Date of Patent: August 12, 1997
    Assignee: Hitachi, Ltd.
    Inventors: Fumikazu Itoh, Toshihiko Nakata, Tohru Ishitani, Akira Shimase, Hiroshi Yamaguchi, Takashi Kamimura