Patents by Inventor Akira Usui

Akira Usui has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6350605
    Abstract: This invention relates to a novel microorganism capable of oxidizing manganese such as the genus Cedecea bacterium GSJ/MITA24A/ASHO-RO/1, the genus Aeromonas bacterium GSJ/MITA24B/ASHO-RO/2, or the genus Shewanella bacterium GSJ/MITA24C/ASHO-RO/3; to a method for removing manganese from water containing manganese, which comprises contacting the water containing manganese with a microbial symbiont of algae and one or more microorganisms capable of oxidizing manganese to oxidize and precipitate the manganese, thereby removing the manganese from the water; and to a method of recycling the recovered manganese.
    Type: Grant
    Filed: December 22, 1999
    Date of Patent: February 26, 2002
    Inventors: Naoki Mita, Yoshishige Kato, Akihiko Maruyama, Takanori Higashihara, Yutaka Kanai, Akira Usui, Hiroyuki Miura, Takashi Ito, Hidetoshi Tashiro
  • Patent number: 6348096
    Abstract: The Group III-V compound semiconductor manufacturing method which pertains to the present invention is a semiconductor manufacturing method employing epitaxy which comprises (a) a step in which growing areas are produced using a mask patterned on a substrate surface and (b) a step in which a Group III-V compound semiconductor layer is grown in the growing areas while forming facet structures. As epitaxy is continued, adjacent facet structures come into contact so that the surface of the semiconductor layer becomes planarized. Since lattice defects extend towards the facet structures, they do not extend towards the surface of the semiconductor layer. Accordingly, the number of lattice defects in the vicinity of the semiconductor layer surface is reduced.
    Type: Grant
    Filed: March 11, 1998
    Date of Patent: February 19, 2002
    Assignee: NEC Corporation
    Inventors: Haruo Sunakawa, Akira Usui
  • Patent number: 6345388
    Abstract: In a television signal transmitting and receiving apparatus, a digitally coded television signal, such as an MPEG2-Video stream, is transmitted, and an accounting level requested by the use is input to the receiver, whereby the decoding coefficient at decoding in an MPEG2-Video decoder is varied to obtain n image having a resolution according to the accounting level. In this apparatus, it is possible to offer a service with a resolution according to the accounting level.
    Type: Grant
    Filed: January 24, 1997
    Date of Patent: February 5, 2002
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Toshiro Nishio, Kiyoshi Imai, Akira Usui
  • Patent number: 6335763
    Abstract: A television receiver receiving an analog video signal, comprises additional information detecting means for separating and extracting an additional information code from the analog video signal, and outputting the additional information code; additional information recording means for recording the additional information code output from the additional information detecting means; additional information writing switch means for passing or blocking the additional information code that is output from the additional information detecting means toward the additional information recording means, in response to a control signal; conversion means for converting the additional information code output from the additional information detecting means or the additional information code reproduced from the additional information recording means into a character or an image; and signal synthesizing means for synthesizing the analog video signal and the additional information that has been converted into a character or an
    Type: Grant
    Filed: January 30, 1997
    Date of Patent: January 1, 2002
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Toshiro Nishio, Kiyoshi Imai, Akira Usui, Kiyokazu Hagiwara
  • Publication number: 20010026950
    Abstract: In a method of manufacturing a semiconductor device by using a sapphire substrate, a nitrogen-based semiconductor thick film is deposited on the sapphire substrate by VPE and is left without any cracks by etching the sapphire substrate by an etchant. The nitrogen-based semiconductor thick film serves as a substrate for manufacturing the semiconductor device.
    Type: Application
    Filed: March 29, 2001
    Publication date: October 4, 2001
    Applicant: NEC Corporation
    Inventors: Haruo Sunakawa, Akira Usui
  • Patent number: 6252261
    Abstract: A GaN crystal film having a mask patterned in a stripe for forming multiple growing areas on a sapphire substrate and coalesced GaN crystals covering the mask dividing the areas, grown from the neighboring growing areas, comprising defects where multiple dislocations along with the stripe are substantially aligned with the normal line of the substrate, in the crystal areas over the mask, and dislocations propagating in substantially parallel with the substrate surface while, in the vicinity of the areas where the crystals are coalesced over the mask, propagating substantially in the normal line of the substrate surface, and a manufacturing process therefor. According to this invention, there can be provided a GaN crystal film in which strain, defects and dislocations are reduced and which tends not to generate cracks.
    Type: Grant
    Filed: June 28, 1999
    Date of Patent: June 26, 2001
    Assignee: NEC Corporation
    Inventors: Akira Usui, Akira Sakai, Haruo Sunakawa, Masashi Mizuta, Yoshishige Matsumoto
  • Patent number: 6183677
    Abstract: An abrasive sheet has an abrasive particle layer formed on a surface of a thin flexible resin film. The abrasive sheet is produced by the steps of preparing a releasable film, forming a thin flexible resin film layer on a release agent applied surface of the releasable film and forming an abrasive particle layer on an upper surface of the resin film layer. Thereafter, the resin film having the abrasive particle layer formed thereon is removed from the releasable film, and the resin film having the abrasive particle layer formed thereon is cut into any suitable size. The abrasive sheet can provide higher polishing power during the polishing operation, but it polishes a surface while tracing or following any orange peel on the surface. Therefore, the abrasive sheet is effective for use as the polishing tool that can replace the fine compound buffing process currently utilized in the automobile repairing industry.
    Type: Grant
    Filed: January 26, 1999
    Date of Patent: February 6, 2001
    Assignee: Kovax Corporation
    Inventors: Akira Usui, Yukio Yoshida
  • Patent number: 5928760
    Abstract: An abrasive sheet has an abrasive particle layer formed on a surface of a thin flexible resin film. The abrasive sheet is produced by the steps of preparing a releasable film, forming a thin flexible resin film layer on a release agent applied surface of the releasable film and forming an abrasive particle layer on an upper surface of the resin film layer. Thereafter, the resin film having the abrasive particle layer formed thereon is removed from the releasable film, and the resin film having the abrasive particle layer formed thereon is cut into any suitable size. The abrasive sheet can provide higher polishing power during the polishing operation, but it polishes a surface while tracing or following any orange peel on the surface. Therefore, the abrasive sheet is effective for use as the polishing tool that can replace the fine compound buffing process currently utilized in the automobile repairing industry.
    Type: Grant
    Filed: September 18, 1996
    Date of Patent: July 27, 1999
    Assignee: Kovax Corporation
    Inventors: Akira Usui, Yukio Yoshida
  • Patent number: 5902393
    Abstract: Disclosed is a method of growing 4 gallium nitride-based crystal by vapor phase epitaxy, suitable for mass production, without the necessity of thermal processing after completion of the crystal growth. The temperature of the substrate crystal immediately after completion of the crystal growth is 700.degree. C. or higher, and cooling of the substrate crystal at 700.degree. C. or lower after completion of the crystal growth is performed in an atmosphere of a hydrogen-fee carrier gas.
    Type: Grant
    Filed: January 17, 1997
    Date of Patent: May 11, 1999
    Assignee: NEC Corporation
    Inventors: Masaaki Nido, Akira Usui, Yasunori Mochizuki
  • Patent number: 5598447
    Abstract: An integrated circuit device is comprised of an input interface, a PLL unit, a processing unit and an output interface. The input interface operates in response to an external clock signal for sequentially receiving input data in synchronization with an external synchro signal. The PLL unit includes an internal clock source operative in phase-locked manner according to the external synchro signal for generating an internal clock signal which is faster than the external clock signal. The processing unit operates in response to the internal clock signal for sequentially processing the input data. The output interface operates in response to the external synchro signal for sequentially outputting the processed data in synchronization with the external synchro signal.
    Type: Grant
    Filed: May 10, 1993
    Date of Patent: January 28, 1997
    Assignee: Yamaha Corporation
    Inventor: Akira Usui
  • Patent number: 5553042
    Abstract: An optical disk recording device capable of recording data by projecting, laser pulse on a disk such as a CD-WO disk on which time information such as ATIP data or address information used for writing is previously recorded while controlling drive of a spindle for rotating the disk by using the information for writing includes a synchronizing signal detection circuit for detecting a synchronizing signal such as an ATIP synchronizing signal from a signal read from the disk, a clock generation circuit for generating a clock from the read out signal by locking PLL (phase lock loop), a counter for counting the clock generated by the clock generation circuit during a period between respective synchronizing signals detected by the synchronizing signal detection circuit, and a slip detection circuit for detecting a slip in the PLL of the clock generation circuit when a count of the counter differs from a predetermined value.
    Type: Grant
    Filed: June 17, 1994
    Date of Patent: September 3, 1996
    Assignee: Yamaha Corporation
    Inventor: Akira Usui
  • Patent number: 5526333
    Abstract: EFM input signal is received via an EFM input interface. Recording-timing adjustment data is received via a computer interface from a computer and stored in a register. To obtain EFM output signal having its pulse duration controlled on the basis of the EFM input signal and the record-timing adjustment data, there are further provided a clock signal generation circuit for generating clock signal by a phase-locked-loop arrangement based on a crystal oscillator, a first pair of counter and comparator driven by the clock signal to determine the pulse duration of a signal to be written, a second pair of counter and comparator that is driven by the clock signal and responsive to the output from the comparator of the first pair to start counting so as to determine a pulse duration to be adjusted, and a flip flop that is reset by the output from the comparator to provide an EFM output signal having a controlled pulse duration.
    Type: Grant
    Filed: May 3, 1994
    Date of Patent: June 11, 1996
    Assignee: Yamaha Corporation
    Inventors: Akira Usui, Katsuichi Osakabe, Yukihisa Nakajo, Yoshihiko Shiozaki
  • Patent number: 5505159
    Abstract: In an epitaxial growth of a group III-V compound semiconductor crystal, there is provided a substrate on which group III element halide molecules are adsorbed. A beam of group V element hydride molecules is supplied toward the substrate for reaction of the group V element hydride and the group III element halide. The vibration energy of each of group V element hydride molecules is excited in the beam and the orientation of the group V element hydride molecules is aligned. As a result, the supplied group V atom directly combines with the group III atom.
    Type: Grant
    Filed: November 17, 1994
    Date of Patent: April 9, 1996
    Assignee: NEC Corporation
    Inventors: Yuji Mochizuki, Akira Usui, Toshikazu Takada
  • Patent number: 5469806
    Abstract: Epitaxial growth is carried out to form crystal such as GaAs, Si, etc. by using GaCl, SiCl.sub.2, etc. In the epitaxial growth, Cl atoms are left on the crystal growth surface. The Cl atoms are removed in the form of HCl molecules by vibrationally-excited H.sub.2 molecules.
    Type: Grant
    Filed: August 20, 1993
    Date of Patent: November 28, 1995
    Assignee: NEC Corporation
    Inventors: Yuji Mochizuki, Yoshie Chiba, Toshikazu Takada, Akira Usui
  • Patent number: 5355532
    Abstract: The present invention relates to a television tuner capable of receiving television broadcasting, CATV and satellite broadcasting. The television tuner includes a double superheterodyne tuner for receiving television signals, having an up-converter, a down-converter and a coupler for coupling the up-converter and down-converter, and the television tuner also includes a BS second mixer portion and a FM demodulator, for receiving signals from a broadcasting satellite. The double superheterodyne tuner, the BS second mixer portion and the FM demodulator are disposed in a housing, a combination of the up-converter and the BS second mixer portion is desiredly separated from the down-converter, the coupler is disposed in a space between the combination and the down-converter, and the FM demodulator is disposed in the remaining space of the housing.
    Type: Grant
    Filed: March 29, 1993
    Date of Patent: October 11, 1994
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kazuhiko Kubo, Akira Usui, Akira Mishima
  • Patent number: 5179729
    Abstract: A tuner station apparatus includes a first mixer for combining an input signal and a first local oscillation signal, and a second mixer for combining an output of the first mixer and a second local oscillation signal. The first and second local oscillation signals are generated by first and second PLL circuits, respectively. Each of the first and second PLL circuits include a frequency divider, a variable frequency divider, a phase comparator, a low pass filter, and a voltage controlled oscillator. The frequency divider of the first PLL circuit has a higher frequency division ratio than that of the second PLL circuit.
    Type: Grant
    Filed: February 20, 1990
    Date of Patent: January 12, 1993
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Akira Mishima, Kazuhiko Kubo, Akira Usui
  • Patent number: 5101369
    Abstract: A digital filter performs a predetermined arithmetic operation on input digital data inputted thereto in time-series manner by the predetermined first sampling period to thereby generate output digital data corresponding to a second sampling frequency which is N (where N denotes an integral number) times larger than the predetermined first sampling frequency. This digital filter provides a synchronizing signal generating circuit and an operation control circuit. The synchronizing signal generating circuit detects the predetermined first sampling period of the input digital data to thereby generate a synchronizing signal having the second sampling frequency. The operation control circuit is activated by its internal clock which is asynchronous with the input digital data. This operation control circuit starts to perform its operation processes when the synchronizing signal is supplied thereto, thereafter it terminates the operation processes when a predetermined step number is completed.
    Type: Grant
    Filed: November 21, 1989
    Date of Patent: March 31, 1992
    Assignee: Yamaha Corporation
    Inventors: Junji Torii, Akira Usui, Lenichi Takeuchi, Masamitsu Yamamura, Yusuke Yamamoto
  • Patent number: 5093922
    Abstract: The present invention relates to a receiving apparatus which can be used in receiving a satellite broadcast by using a cable television system. The receiving apparatus uses a double-super type converter or tuner (2) having a first frequency-conversion portion (15) and a second frequency-conversion portion (19). A conversion output terminal (G) for feeding a signal to a BS tuner (5) is provided at the output side of the first frequency-conversion portion (15). A BA signal converted into a UHF band or a superhigh band is fed to the first frequency-conversion portion (15) through a cable, so that, after frequency conversion, a BS-IF signal is taken out from the conversion output terminal (G). Thus, the BS-IF signal can be fed to the BS tuner (5) without using any special up-converter.
    Type: Grant
    Filed: July 18, 1989
    Date of Patent: March 3, 1992
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kazuhiko Kubo, Akira Usui, Minoru Ueda
  • Patent number: 5014349
    Abstract: The invention relates to a television receiving tuner for receiving television signals of VHF band/UHF band, a CATV signal, and a satellite television broadcasting signal. As a circuit for receiving the television signals of the VHF band/UHF band and the CATV signal as a first input signal, there is provided a double super type tuner of the up/down converter system including a first local oscillator (6) and a first mixer (5) which construct an up converter and a second local oscillator (10) and a second mixer (9) which construct a down converter. When the satellite television broadcasting signal as a second input signal is received, the first local oscillator (6) and the first mixer (5) in the up converter section are switched by switching circuits (12, 13) and used as a down converter.
    Type: Grant
    Filed: August 14, 1989
    Date of Patent: May 7, 1991
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kazuhiko Kubo, Akira Usui, Seiji Sakashita, Hiroaki Ozeki, Ippei Kanno
  • Patent number: 4866648
    Abstract: A digital filter of an FIR (non-recursive) type operating as an oversampling filter in digital signal processing such as for a stereophonic audio device comprises a memory storing impulse response coefficient data, a mantissa data producing circuit for converting the coefficient data to mantissa data, a multiplier for multiplying input data with the mantissa data, an accumulator for accumulating output data of the multiplier, and a bit-shifting circuit for bit-shifting accumulated output data of the accumulator by the number of bits substantially corresponding to the change in the number of bits of exponent data in the coefficient data. The mantissa data is combined with input data in the convolution operation and the exponent data is imparted, in accumulation of multiplied values, by the bit-shifting of the accumulation output data. In one aspect of the invention, the bit-shifting is performed in a decreasing direction starting from the coefficient of the smallest exponent.
    Type: Grant
    Filed: September 28, 1987
    Date of Patent: September 12, 1989
    Assignee: Yamaha Corporation
    Inventor: Akira Usui