Patents by Inventor Alain Artieri
Alain Artieri has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11907138Abstract: Various embodiments include methods and devices for implementing a criterion aware cache replacement policy by a computing device. Embodiments may include updating a staling counter, writing a value of a local counter to a system cache in association with a location in the system cache for with data, in which the value of the local counter includes a value of the staling counter when (i.e., at the time) the associated data is written to the system cache, and using the value of the local counter of the associated data to determine whether the associated data is stale.Type: GrantFiled: December 31, 2021Date of Patent: February 20, 2024Assignee: QUALCOMM IncorporatedInventors: Hiral Nandu, Subbarao Palacharla, George Patsilaras, Alain Artieri, Simon Peter William Booth, Vipul Gandhi, Girish Bhat, Yen-Kuan Wu, Younghoon Kim
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Publication number: 20230214330Abstract: Various embodiments include methods and devices for implementing a criterion aware cache replacement policy by a computing device. Embodiments may include updating a staling counter, writing a value of a local counter to a system cache in association with a location in the system cache for with data, in which the value of the local counter includes a value of the staling counter when (i.e., at the time) the associated data is written to the system cache, and using the value of the local counter of the associated data to determine whether the associated data is stale.Type: ApplicationFiled: December 31, 2021Publication date: July 6, 2023Inventors: Hiral NANDU, Subbarao PALACHARLA, George PATSILARAS, Alain ARTIERI, Simon Peter William BOOTH, Vipul GANDHI, Girish BHAT, Yen-Kuan WU, Younghoon KIM
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Patent number: 11520706Abstract: Data caching may include storing data associated with DRAM transaction requests in data storage structures organized in a manner corresponding to the DRAM bank, bank group and rank organization. Data may be selected for transfer to the DRAM by selecting among the data storage structures.Type: GrantFiled: April 29, 2021Date of Patent: December 6, 2022Assignee: QUALCOMM IncorporatedInventors: Alain Artieri, Rakesh Kumar Gupta, Subbarao Palacharla, Kedar Bhole, Laurent Rene Moll, Carlo Spitale, Sparsh Singhai, Shyamkumar Thoziyoor, Gopi Tummala, Christophe Avoinne, Samir Ginde, Syed Minhaj Hassan, Jean-Jacques Lecler, Luigi Vinci
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Publication number: 20220350749Abstract: Data caching may include storing data associated with DRAM transaction requests in data storage structures organized in a manner corresponding to the DRAM bank, bank group and rank organization. Data may be selected for transfer to the DRAM by selecting among the data storage structures.Type: ApplicationFiled: April 29, 2021Publication date: November 3, 2022Inventors: Alain ARTIERI, Rakesh Kumar GUPTA, Subbarao PALACHARLA, Kedar BHOLE, Laurent Rene MOLL, Carlo SPITALE, Sparsh SINGHAI, Shyamkumar THOZIYOOR, Gopi TUMMALA, Christophe AVOINNE, Samir GINDE, Syed Minhaj HASSAN, Jean-Jacques LECLER, Luigi VINCI
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Patent number: 11403217Abstract: Memory utilization in an SDRAM system may be improved by increasing memory bank group and memory bank interleaving. Memory bank group interleaving and memory bank interleaving may be increased by a memory controller generating a physical memory address in which the bank group address bits are positioned nearer the LSB of the physical memory address than the MSB. Alternatively, or in addition to positioning the bank group address bits in such a manner, memory bank group interleaving and memory bank interleaving may be increased by hashing the bank group address bits and bank address bits of the physical memory address with row address bits of the initial physical memory address, A rank address bit may also be involved in the hashing.Type: GrantFiled: March 18, 2020Date of Patent: August 2, 2022Assignee: QUALCOMM IncorporatedInventors: Alain Artieri, Jean-Jacques Lecler, Shyamkumar Thoziyoor
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Patent number: 11281526Abstract: Disclosed are techniques for generating a parity check matrix representing an error correcting code (ECC) for protecting a plurality of bits of a message. In an aspect, a method includes initializing a matrix M to store selected three-bit codes, selecting a first three-bit code from a set L of three-bit combinations of a number of bits n of the ECC that minimizes a sum of squared row weights of each row of the matrix M, comparing the first three-bit code with each of a plurality of error syndromes, and calculating, based on no comparison of the first three-bit code with each of the plurality of error syndromes, new error syndromes and storing the new error syndromes, wherein the new error syndromes are calculated by comparing the first three-bit code with each three-bit code in the matrix M, and storing the first three-bit code in the matrix M.Type: GrantFiled: August 31, 2020Date of Patent: March 22, 2022Assignee: QUALCOMM IncorporatedInventors: Alain Artieri, Deepti Vijayalakshmi Sriramagiri, Dexter Tamio Chun, Jungwon Suh
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Patent number: 11126431Abstract: A method for dynamic memory scheduling with enhanced bank-group batching is described. The method includes determining a read-bank group-spread of each rank, as a number of bank-groups of each respective rank targeted by at least one read instruction. The method further includes determining a write-bank group-spread of each rank, as a number of bank-groups of each rank targeted by at least one write instruction. The method also includes stalling a current batch of read instructions in a rank when the read-bank group-spread of the rank is less than a predetermined value. The method further includes stalling a current batch of write instructions in a rank when the write-bank group-spread of the rank is less than the predetermined value.Type: GrantFiled: May 29, 2020Date of Patent: September 21, 2021Assignee: QUALCOMM IncorporatedInventors: Jean-Jacques Lecler, Alain Artieri
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Publication number: 20210133100Abstract: Memory utilization in an SDRAM system may be improved by increasing memory bank group and memory bank interleaving. Memory bank group interleaving and memory bank interleaving may be increased by a memory controller generating a physical memory address in which the bank group address bits are positioned nearer the LSB of the physical memory address than the MSB. Alternatively, or in addition to positioning the bank group address bits in such a manner, memory bank group interleaving and memory bank interleaving may be increased by hashing the bank group address bits and bank address bits of the physical memory address with row address bits of the initial physical memory address, A rank address bit may also be involved in the hashing.Type: ApplicationFiled: March 18, 2020Publication date: May 6, 2021Inventors: Alain ARTIERI, Jean-Jacques LECLER, Shyamkumar THOZIYOOR
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Patent number: 10922168Abstract: Errors can be introduced when data is transferred over a link between two entities such as between a host and a memory. Link error protection schemes can be implemented to detect and correct errors that occur on the link to enhance transmission reliability. However, these benefits are not without costs since such protection schemes increase both latency and power consumption. In one or more aspects, it is proposed to dynamically adjust the level of link error protection applied to match any change in the operating environment. For example, likelihood of link errors strongly correlates with the link speed. If the link speed is increased, a greater level of link error protection can be applied to counteract the increase in the link errors. If the link speed is decreased, the level of protection can be decreased so that latency and power consumption penalties can be minimized.Type: GrantFiled: July 3, 2019Date of Patent: February 16, 2021Assignee: QUALCOMM IncorporatedInventors: Jungwon Suh, Alain Artieri, Dexter Tamio Chun, Deepti Vijayalakshmi Sriramagiri
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Publication number: 20200401474Abstract: Disclosed are techniques for generating a parity check matrix representing an error correcting code (ECC) for protecting a plurality of bits of a message. In an aspect, a method includes initializing a matrix M to store selected three-bit codes, selecting a first three-bit code from a set L of three-bit combinations of a number of bits n of the ECC that minimizes a sum of squared row weights of each row of the matrix M, comparing the first three-bit code with each of a plurality of error syndromes, and calculating, based on no comparison of the first three-bit code with each of the plurality of error syndromes, new error syndromes and storing the new error syndromes, wherein the new error syndromes are calculated by comparing the first three-bit code with each three-bit code in the matrix M, and storing the first three-bit code in the matrix M.Type: ApplicationFiled: August 31, 2020Publication date: December 24, 2020Inventors: Alain ARTIERI, Deepti Vijayalakshmi SRIRAMAGIRI, Dexter Tamio CHUN, Jungwon SUH
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Patent number: 10853163Abstract: Disclosed are techniques for generating a parity check matrix representing an error correcting code (ECC) for protecting a plurality of bits of a message. In an aspect, a method includes initializing a matrix M to store selected three-bit codes, selecting a first three-bit code from a set L of three-bit combinations of a number of bits n of the ECC that minimizes a sum of squared row weights of each row of the matrix M, comparing the first three-bit code with each of a plurality of error syndromes, and calculating, based on no comparison of the first three-bit code with each of the plurality of error syndromes, new error syndromes and storing the new error syndromes, wherein the new error syndromes are calculated by comparing the first three-bit code with each three-bit code in the matrix M, and storing the first three-bit code in the matrix M.Type: GrantFiled: March 30, 2018Date of Patent: December 1, 2020Assignee: QUALCOMM IncorporatedInventors: Alain Artieri, Deepti Vijayalakshmi Sriramagiri, Dexter Tamio Chun, Jungwon Suh
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Publication number: 20190324850Abstract: Errors can be introduced when data is transferred over a link between two entities such as between a host and a memory. Link error protection schemes can be implemented to detect and correct errors that occur on the link to enhance transmission reliability. However, these benefits are not without costs since such protection schemes increase both latency and power consumption. In one or more aspects, it is proposed to dynamically adjust the level of link error protection applied to match any change in the operating environment. For example, likelihood of link errors strongly correlates with the link speed. If the link speed is increased, a greater level of link error protection can be applied to counteract the increase in the link errors. If the link speed is decreased, the level of protection can be decreased so that latency and power consumption penalties can be minimized.Type: ApplicationFiled: July 3, 2019Publication date: October 24, 2019Inventors: Jungwon SUH, Alain ARTIERI, Dexter Tamio CHUN, Deepti Vijayalakshmi SRIRAMAGIRI
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Patent number: 10387242Abstract: Errors can be introduced when data is transferred over a link between two entities such as between a host and a memory. Link error protection schemes can be implemented to detect and correct errors that occur on the link to enhance transmission reliability. However, these benefits are not without costs since such protection schemes increase both latency and power consumption. In one or more aspects, it is proposed to dynamically adjust the level of link error protection applied to match any change in the operating environment. For example, likelihood of link errors strongly correlates with the link speed. If the link speed is increased, a greater level of link error protection can be applied to counteract the increase in the link errors. If the link speed is decreased, the level of protection can be decreased so that latency and power consumption penalties can be minimized.Type: GrantFiled: August 21, 2017Date of Patent: August 20, 2019Assignee: QUALCOMM IncorporatedInventors: Jungwon Suh, Alain Artieri, Dexter Tamio Chun, Deepti Vijayalakshmi Sriramagiri
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Patent number: 10254823Abstract: An integrated circuit (IC) is disclosed herein for power management using duty cycles. In an example aspect, the integrated circuit includes multiple power domains, each of which includes a respective power state controller. The power state controller acts as a bridge between global supply lines of the integrated circuit and local supply lines of the respective power domain. Global supply lines can include a first global power rail, a second global power rail, and a global clock tree. Local supply lines can include a local power rail and a local clock tree. In operation, a power state controller adjusts a power state of the respective power domain in accordance with a duty cycle. A timeslot corresponding to the duty cycle can be separated into multiple time periods with durations of the time periods being based on the duty cycle.Type: GrantFiled: March 28, 2017Date of Patent: April 9, 2019Assignee: QUALCOMM IncorporatedInventors: Alain Artieri, Jean-Marie Tran
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Publication number: 20190056990Abstract: Errors can be introduced when data is transferred over a link between two entities such as between a host and a memory. Link error protection schemes can be implemented to detect and correct errors that occur on the link to enhance transmission reliability. However, these benefits are not without costs since such protection schemes increase both latency and power consumption. In one or more aspects, it is proposed to dynamically adjust the level of link error protection applied to match any change in the operating environment. For example, likelihood of link errors strongly correlates with the link speed. If the link speed is increased, a greater level of link error protection can be applied to counteract the increase in the link errors. If the link speed is decreased, the level of protection can be decreased so that latency and power consumption penalties can be minimized.Type: ApplicationFiled: August 21, 2017Publication date: February 21, 2019Inventors: Jungwon SUH, Alain ARTIERI, Dexter Tamio CHUN, Deepti Vijayalakshmi SRIRAMAGIRI
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Patent number: 10180908Abstract: Aspects include computing devices, systems, and methods for implementing a cache maintenance or status operation for a component cache of a system cache. A computing device may generate a component cache configuration table, assign at least one component cache indicator of a component cache to a master of the component cache, and map at least one control register to the component cache indicator by a centralized control entity. The computing device may store the component cache indicator such that the component cache indicator is accessible by the master of the component cache for discovering a virtualized view of the system cache and issuing a cache maintenance or status command for the component cache bypassing the centralized control entity. The computing device may receive the cache maintenance or status command by a control register associated with a cache maintenance or status command and the component cache bypassing the centralized control entity.Type: GrantFiled: May 13, 2015Date of Patent: January 15, 2019Assignee: QUALCOMM IncorporatedInventors: Yanru Li, Subbarao Palacharla, Moinul Khan, Alain Artieri, Azzedine Touzni
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Publication number: 20180314586Abstract: Disclosed are techniques for generating a parity check matrix representing an error correcting code (ECC) for protecting a plurality of bits of a message. In an aspect, a method includes initializing a matrix M to store selected three-bit codes, selecting a first three-bit code from a set L of three-bit combinations of a number of bits n of the ECC that minimizes a sum of squared row weights of each row of the matrix M, comparing the first three-bit code with each of a plurality of error syndromes, and calculating, based on no comparison of the first three-bit code with each of the plurality of error syndromes, new error syndromes and storing the new error syndromes, wherein the new error syndromes are calculated by comparing the first three-bit code with each three-bit code in the matrix M, and storing the first three-bit code in the matrix M.Type: ApplicationFiled: March 30, 2018Publication date: November 1, 2018Inventors: Alain ARTIERI, Deepti Vijayalakshmi SRIRAMAGIRI, Dexter Tamio CHUN, Jungwon SUH
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Publication number: 20180284878Abstract: An integrated circuit (IC) is disclosed herein for power management using duty cycles. In an example aspect, the integrated circuit includes multiple power domains, each of which includes a respective power state controller. The power state controller acts as a bridge between global supply lines of the integrated circuit and local supply lines of the respective power domain. Global supply lines can include a first global power rail, a second global power rail, and a global clock tree. Local supply lines can include a local power rail and a local clock tree. In operation, a power state controller adjusts a power state of the respective power domain in accordance with a duty cycle. A timeslot corresponding to the duty cycle can be separated into multiple time periods with durations of the time periods being based on the duty cycle.Type: ApplicationFiled: March 28, 2017Publication date: October 4, 2018Inventors: Alain Artieri, Jean-Marie Tran
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Patent number: 10089238Abstract: Aspects include computing devices, systems, and methods for dynamically partitioning a system cache by sets and ways into component caches. A system cache memory controller may manage the component caches and manage access to the component caches. The system cache memory controller may receive system cache access requests and reserve locations in the system cache corresponding to the component caches correlated with component cache identifiers of the requests. Reserving locations in the system cache may activate the locations in the system cache for use by a requesting client, and may also prevent other client from using the reserved locations in the system cache. Releasing the locations in the system cache may deactivate the locations in the system cache and allow other clients to use them. A client reserving locations in the system cache may change the amount of locations it has reserved within its component cache.Type: GrantFiled: July 17, 2014Date of Patent: October 2, 2018Assignee: QUALCOMM IncorporatedInventors: Subbarao Palacharla, Moinul Khan, Alain Artieri, Kedar Bhole, Vinod Chamarty, Yanru Li, Raghu Sankuratri, George Patsilaras, Pavan Kumar Thirunagari, Andrew Edmund Turner, Jeong-Ho Woo
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Patent number: 9785371Abstract: Systems, methods, and computer programs are disclosed for method for reducing memory subsystem power. In an exemplary method, a system resource manager provides memory performance requirements for a plurality of memory clients to a double data rate (DDR) subsystem. The DDR subsystem and the system resource manager reside on a system on chip (SoC) electrically coupled to a dynamic random access memory (DRAM). A cache hit rate is determined of each of the plurality of memory clients associated with a system cache residing on the DDR subsystem. The DDR subsystem adjusts access to the DRAM based on the memory performance requirements received from the system resource manager and the cache hit rates of the plurality of memory clients.Type: GrantFiled: March 27, 2016Date of Patent: October 10, 2017Assignee: QUALCOMM IncorporatedInventors: Yanru Li, Dexter Tamio Chun, Alain Artieri