Abstract: A system for converting digital television signals encoded according to an MPEG standard into standardized analog video signals. The system includes means for generating graphic images and for inserting corresponding image signals in a decoded digital flow of main image signals, a digital decoding unit, and an analog coding unit. The digital decoding unit includes means for providing a flow of multiplexed image signals including a first flow of main image signals and of a second flow of image signals that contains, in addition to the main image signals, possible graphic image signals. The analog coding unit includes a demultiplexer of the flow of multiplexed image signals and two encoders. The two encoders respectively receive the first and second flows, and each respectively provide a digital flow of images encoded according to a color television standard to digital-to-analog converters respectively associated therewith, the digital-to-analog converters providing the standardized analog video signals.

Abstract: A dual-port memory includes a dummy memory cell associated with a dummy output line and with a precharge transistor, the output of the dummy cell being at "0". A dummy read transistor is turned on by the active state of the read selection signal and connects the output of the dummy cell to the dummy output line. Circuitry is provided for turning on the output transistors of the memory when the state of the dummy output line reaches a predetermined switching threshold of an inverter.

Abstract: A memory for storing a reorganizing array of an initial array of data of binary ones and zeros to enable decoding of the reorganized array to reproduce the information content of the initial array, and the method of reorganizing the initial array. The memory includes a data circuit array that has a plurality of memory cells arranged in rows and columns for storing the reorganized array. The memory also has a plurality of flag memory cells and a row of XOR gates and inverters. The initial array is divided into sections. Each row of each section of the initial array that has more ones than zeros is inverted, and the corresponding flag bit is also inverted. Each column of the initial array that has more ones than zeros is inverted, and the corresponding flag bit is also inverted. This is repeated until each row in each section and each column has at least as many ones as zeros, producing the reorganized array.

Abstract: A four transistor dynamic memory cell architecture and refresh technique which allows for cell refresh to occur during a read operation. The access and memory transistors of the individual memory cells are fabricated with a relative width-to-length ratio such that it is sufficient to merely activate the associated word line to perform the refresh operation. This is accomplished without activating the read sense amplifier resulting in lower power consumption and the retention of most recently read data. Multiple word lines may be activated concurrently utilizing the technique disclosed to further reduce the refresh rate overhead in a memory array and increase the overall memory array bandwidth.

Abstract: A system incorporates a processor that includes a data bus having a fixed N-bits size connected to an n-bits word memory through a bus having an n-bits size, where N is a multiple of n, and n is a variable value. The system includes means for, at each execution by the processor of a write instruction of one word of N bits in the memory, successively writing each sub-word of n bits constituting this word of N bits at distinct addresses, and means for, at each execution of a read instruction of a word of N bits in the memory, successively reading in this memory at distinct addresses sub-words of n bits, and juxtaposing these sub-words on the fixed size bus.

Abstract: A data reorganization process includes a dual-port memory coupled to a system for writing words in a first predetermined order and for reading the words in a second predetermined order. A register cooperates with the circuit authorizing reading of the words only if the content of the register is non-zero. The content of the register is decremented at each read and incremented at each write. The increment is equal to one plus the difference between the input rank of the current word provided on the first bus and the output rank of this word if the difference is non-negative, and whose value is zero if the difference is negative. The effective value of this increment is such that the sum of the increments that are used until the writing of the current word is written is lower than, or equal to, the sum of the optimum values of these used increments.

Abstract: A pixel matrix filter includes n input buses to receive pixels of n successive columns of the matrix; n delay circuits respectively receiving the pixels from the n input buses, each of these delay circuits introducing a delay of one column, whereby 2n pixels are simultaneously transmitted to the outputs of the n delay circuits and to the n input buses, successively; and n adders connected at least so that the i-th adder receives the i-th of the 2n pixels at a first input and the (i+1)th of the 2n pixels at a second input.

Abstract: A processor architecture for executing a current task among a plurality of possible tasks. The architecture includes: a plurality of instruction pointers respectively associated with the tasks and each storing the address of the current instruction to be executed of the associated task, only one of these pointers being enabled at a time to supply an address to the memory; a priority level decoder including circuitry for assigning a predetermined priority level to each request signal and for enabling the instruction pointer associated with the active request signal having the highest priority level; and a mechanism for incrementing the content of the enabled instruction pointer and for reinitializing it at the start address of the associated program when its content reaches the end address of the associated program.

Abstract: A system that processes compressed data arriving in packets corresponding to picture blocks, the packets being separated by headers containing decoding parameters of the packets. A memory bus is controlled by a memory controller to exchange data between the processing elements and a picture memory. A pipeline circuit contains a plurality of processing elements. A parameter bus provides packets to be processed to the pipeline circuit, as well as the decoding parameters to elements of the system. The parameter bus is controlled by a variable length decoder that receives the compressed data from the memory bus and that extracts the packets and the decoding parameters therefrom.

Abstract: A method for sorting the k greatest ones of a sequence of n incoming data values, by: a) sequentially writing each data value into one of n one-word memories, in a word format which includes, in decreasing weight order, the following bits: a first inhibition bit (MI), a second selection bit (MS), third data bits (MD), and fourth bits (MP) representative of the position of the incoming datum; b) setting the first bits (MI) of the n words during the arrival of the first signal; c) while writing each data value, resetting the first (MI) and second (MS) bits of the corresponding word; and d) between the arrivals of the (n-k).sup.th datum and n.sup.th datum, detecting the smallest word stored in the memories and setting its second bit (MS).

Abstract: A data shuffler of the pipeline type receives successive trains of n sequential data words and rearranges data words in each train according to a predetermined order. It comprises p (p.ltoreq.n) elementary processing units arranged in series. Each unit comprises an input, an output, a one-word storage register (20), a steering means (21) in order, in response to a binary control, to connect the input to the output either directly or through the register; and means for periodically supplying to each of the p steering means a sequence of n control bits determined as a function of said predetermined order.

Abstract: A device for converting a horizontal scanning of successive lines of N data into a saw tooth scanning of stripes having a height of M lines. This device comprises a MN word memory wherein are sequentially written the first MN data, then wherein the following data are sequentially written while the existing data are read out at same successive addresses A.sub.i,j. The value of i determines the sequence number of the data of the memory (0<i<MN-1), and the value of j determines a stripe number (1<j<n). An address generator supplies addresses A.sub.i,j so that A.sub.i+1,j =(A.sub.i,j +x.sub.j) Modulo(MN-1), x.sub.j being a number such that x.sub.j+1 =N.x.sub.j Modulo(MN-1) and x.sub.j =1.

Abstract: A circuit for generating non-overlapping complementary clock signals at a double frequency from an input clock signal. An NAND flip-flop (2) has complementary outputs on which double frequency signals are available. A D-type flip-flop (3) receives on its clock input (H) one of the outputs of the NAND flip-flop, and has its output (Q.sub.D) coupled to its data input (D) through an inverter. Two Exclusive OR gates (XO1, XO2) receive on their first inputs the input clock signal and its complement, respectively, and on their second input the output of the D-type flip-flop. The outputs of the OR gates are connected to the inputs (E1 and E2) of the NAND flip-flop, respectively.

Abstract: A serializer/deserializer for a flow of n-bits of data shifted according to the rate of a clock includes an n-rows and n-columns matrix of 1-bit registers (00-77). Each 1-bit register is connected through its input to a first switch connected to the output of the register in the same row and lower rank column and to a second switch connected to the output of the register in the same column and upper rank row. Input terminals (E0-E7) are connected to the registers of the lower rank column and of the upper rank row. Output terminals (S0-S7) are connected to the registers of the upper rank column and of the lower rank row. The matrix cells are arranged according to a triangle, the cells being arranged one with respect to the other according to the structural corresponding to folding a square matrix along its diagonal.

Abstract: For processing data signals representative of pixels, each of the pictures s scanned, column per column in successive horizontal bands each having a height equal to an entire fraction of the height of the picture, whereby a representation of the picture as pixels distributed in rows and columns is obtained, each band having a common predetermined number of rows. The picture is fractionated into mutually adjacent blocks of pixels each having M pixels in each of N mutually adjacent columns, M and N being predetermined integers and M being a simple multiple of the number of pixels in one column of a band and N being a whole fraction of the number of colums per image.

Abstract: For filtering a bi-dimensional image signal in the form of data representing pixels obtained by column per column scanning of bands each having a height equal to a fraction of the height of the image, the transform of each pixel is computed in turn. For that, a convolution product using MxN coefficients is carried out on the pixels of a zone of an image, each column of each M pixels. The image is fractionated into mutually adjacent blocks each representing N columns of M pixels and the transforms of all pixels of a same block are simultaneously computed in MxN cycles by: parallel computation, during a same cycle, of all partial convolution products of only one of the filtering coefficients and of those pixels which provide a partial product which intervenes in the computation of the transforms of all pixels of the block, within a "window" of the picture which contains the block. The cycle is repeated for each coefficient in turn. All partial products obtained during the successive cycles are summed.

Abstract: A memory of n.times.n digital data, is adapted to receive the n.times.n data from a matrix block in line order after line and to output the data in column after column order. Such a memory is particularly useful for circuits carrying out digital transformations such as cosinus transformations wherein one must first carry out a line transformation then a column summation.The memory is constituted by a network of n.times.n registers REG(i,j) and of n.times.n multiplexers MUX(i,j); the registers are operated at a period T and the multiplexers at a period n.times.T. The connections between the memory inputs and outputs and the register network are alternatively connected at the period n.times.T in order that in a first phase the data are introduced and "horizontally" shifted inside the network and that in a second phase the data are introduced and "vertically" shifted.

Abstract: A signal-processing circuit performs a cosine type transformation (double addition in rows and columns) of values of a matrix of n rows and n columns. An architecture is proposed with a row transform circuit, a column transform circuit and a buffer memory of nxn words. The memory is addressed sequentially, line by line, during the storage of nxn coefficients C.sup.i (v) which are the results of the row transform on a block of nxn data. Then it is addressed sequentially, column by column, during the storage of nxn coefficients C.sup.i (v) corresponding to the processing of the following block. At each address, a read stage of a coefficient is performed followed by the writing of a new coefficient. The invention can be applied to circuits for the digital processing of images to prepare the compression of data before transmission.

Abstract: A data shuffler of the pipeline type receives successive trains of n sequential data words and rearranges data words in each train according to a predetermined order. It comprises p (p.ltoreq.n) elementary processing units arranged in series. Each unit comprises an input, an output, a one-word storage register (20), a steering means (21) in order, in response to a binary control, to connect the input to the output either directly or through the register; and means for periodically supplying to each of the p steering means a sequence of n control bits determined as a function of said predetermined order.