Patents by Inventor Alan B. Botula
Alan B. Botula has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8890246Abstract: Integrated circuits having doped bands in a substrate and beneath high-voltage semiconductor-on-insulator (SOI) devices are provided. In one embodiment, the invention provides an integrated circuit comprising: a semiconductor-on-insulator (SOI) wafer including: a substrate; a buried oxide (BOX) layer atop the substrate; and a semiconductor layer atop the BOX layer; a plurality of high voltage (HV) devices connected in series within the semiconductor layer; a doped band within the substrate and below a first of the plurality of HV devices; and a contact extending from the semiconductor layer and through the BOX layer to the doped band.Type: GrantFiled: August 28, 2012Date of Patent: November 18, 2014Assignee: International Business Machines CorporationInventors: Alan B. Botula, Beth Ann Rainey, Yun Shi
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Patent number: 8866226Abstract: At least one conductive via structure is formed from an interconnect-level metal line through a middle-of-line (MOL) dielectric layer, a shallow trench isolation structure in a top semiconductor layer, and a buried insulator layer to a bottom semiconductor layer. The shallow trench isolation structure laterally abuts at least two field effect transistors that function as a radio frequency (RF) switch. The at least one conductive via structure and the at interconnect-level metal line may provide a low resistance electrical path from the induced charge layer in a bottom semiconductor layer to electrical ground, discharging the electrical charge in the induced charge layer. The discharge of the charge in the induced charge layer thus reduces capacitive coupling between the semiconductor devices and the bottom semiconductor layer, and thus secondary coupling between components electrically disconnected by the RF switch is reduced.Type: GrantFiled: January 9, 2012Date of Patent: October 21, 2014Assignee: International Business Machines CorporationInventors: Alan B. Botula, Alvin J. Joseph, Edward J. Nowak, Yun Shi, James A. Slinkman
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Publication number: 20140306325Abstract: A silicon device includes an active silicon layer, a buried oxide (BOX) layer beneath the active silicon layer and a high-resistivity silicon layer beneath the BOX layer. The device also includes a harmonic suppression layer at a boundary of the BOX layer and the high-resistivity silicon layer.Type: ApplicationFiled: June 24, 2014Publication date: October 16, 2014Inventors: Alan B. Botula, Mark D. Jaffe, Alvin J. Joseph, Richard A. Phelps, James Slinkman, Randy L. Wolf
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Patent number: 8828746Abstract: A silicon device includes an active silicon layer, a buried oxide (BOX) layer beneath the active silicon layer and a high-resistivity silicon layer beneath the BOX layer. The device also includes a harmonic suppression layer at a boundary of the BOX layer and the high-resistivity silicon layer.Type: GrantFiled: November 14, 2012Date of Patent: September 9, 2014Assignee: International Business Machines CorporationInventors: Alan B. Botula, Mark D. Jaffe, Alvin J. Joseph, Richard A. Phelps, James Slinkman, Randy L. Wolf
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Publication number: 20140213036Abstract: A substrate includes a first region having a first resistivity, for optimizing a field effect transistor, a second region having a second resistivity, for optimizing an npn subcollector of a bipolar transistor device and triple well, a third region having a third resistivity, with a high resistivity for a passive device, a fourth region, substantially without implantation, to provide low perimeter capacitance for devices.Type: ApplicationFiled: March 31, 2014Publication date: July 31, 2014Applicant: International Business Machines CorporationInventors: Alan B. Botula, Renata Camillo-Castillo, James S. Dunn, Jeffrey P. Gambino, Douglas B. Hershberger, Alvin J. Joseph, Robert M. Rassel, Mark E. Stidham
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Publication number: 20140191322Abstract: An approach for sinking heat from a transistor is provided. A method includes forming a substrate contact extending from a first portion of a silicon-on-insulator (SOI) island to a substrate. The method also includes forming a transistor in a second portion of the SOI island. The method further includes electrically isolating the substrate contact from the transistor by doping the first portion of the SOI island.Type: ApplicationFiled: January 10, 2013Publication date: July 10, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Alan B. BOTULA, Alvin J. JOSEPH, James A. SLINKMAN, Randy L. WOLF
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Patent number: 8748285Abstract: A semiconductor structure includes a semiconductor-on-insulator substrate, the semiconductor-on-insulator substrate comprising a handle wafer, a buried oxide (BOX) layer on top of the handle wafer, and a top silicon layer on top of the BOX layer; and an implantation region located in the top silicon layer, the implantation region comprising a noble gas.Type: GrantFiled: November 28, 2011Date of Patent: June 10, 2014Assignee: International Business Machines CorporationInventors: Alan B. Botula, William F. Clark, Jr., Richard A. Phelps, BethAnn Rainey, Yun Shi, James A. Slinkman
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Patent number: 8741739Abstract: A semiconductor structure and a method of forming the same. In one embodiment, a method of forming a silicon-on-insulator (SOI) wafer substrate includes: providing a handle substrate; forming a high resistivity material layer over the handle substrate, the high resistivity material layer including one of an amorphous silicon carbide (SiC), a polycrystalline SiC, an amorphous diamond, or a polycrystalline diamond; forming an insulator layer over the high resistivity material layer; and bonding a donor wafer to a top surface of the insulator layer to form the SOI wafer substrate.Type: GrantFiled: January 3, 2012Date of Patent: June 3, 2014Assignee: International Business Machines CorporationInventors: Alan B. Botula, Mark D. Jaffe, Alvin J. Joseph
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Patent number: 8735986Abstract: A substrate includes a first region having a first resistivity, for optimizing a field effect transistor, a second region having a second resistivity, for optimizing an npn subcollector of a bipolar transistor device and triple well, a third region having a third resistivity, with a high resistivity for a passive device, a fourth region, substantially without implantation, to provide low perimeter capacitance for devices.Type: GrantFiled: December 6, 2011Date of Patent: May 27, 2014Assignee: International Business Machines CorporationInventors: Alan B. Botula, Renata Camillo-Castillo, James S. Dunn, Jeffrey P. Gambino, Douglas B. Hershberger, Alvin J. Joseph, Robert M. Rassel, Mark E. Stidham
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Publication number: 20140131800Abstract: A silicon device includes an active silicon layer, a buried oxide (BOX) layer beneath the active silicon layer and a high-resistivity silicon layer beneath the BOX layer. The device also includes a harmonic suppression layer at a boundary of the BOX layer and the high-resistivity silicon layer.Type: ApplicationFiled: November 14, 2012Publication date: May 15, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Alan B. Botula, Mark D. Jaffe, Alvin J. Joseph, Richard A. Phelps, James Slinkman, Randy L. Wolf
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Patent number: 8722508Abstract: A low harmonic radio-frequency (RF) switch in a silicon-on-insulator (SOI) substrate and methods of manufacture. A method includes forming at least one trench through an insulator layer. The at least one trench is adjacent a device formed in an active region on the insulator layer. The method also includes forming at least one cavity in a substrate under the insulator layer and extending laterally from the at least one trench to underneath the device.Type: GrantFiled: March 15, 2013Date of Patent: May 13, 2014Assignee: International Business Machines CorporationInventors: Alan B. Botula, Dinh Dang, James S. Dunn, Alvin J. Joseph, Peter J. Lindgren
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Publication number: 20140124902Abstract: A semiconductor structure and a method of forming the same. In one embodiment, a method of forming a silicon-on-insulator (SOI) wafer substrate includes: providing a handle substrate; forming a high resistivity material layer over the handle substrate, the high resistivity material layer including one of an amorphous silicon carbide (SiC), a polycrystalline SiC, an amorphous diamond, or a polycrystalline diamond; forming an insulator layer over the high resistivity material layer; and bonding a donor wafer to a top surface of the insulator layer to form the SOI wafer substrate.Type: ApplicationFiled: January 9, 2014Publication date: May 8, 2014Applicant: International Business Machines CorporationInventors: Alan B. Botula, Mark D. Jaffe, Alvin J. Joseph
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Patent number: 8709903Abstract: Disclosed is semiconductor structure with an insulator layer on a semiconductor substrate and a device layer is on the insulator layer. The substrate is doped with a relatively low dose of a dopant having a given conductivity type such that it has a relatively high resistivity. Additionally, a portion of the semiconductor substrate immediately adjacent to the insulator layer can be doped with a slightly higher dose of the same dopant, a different dopant having the same conductivity type or a combination thereof. Optionally, micro-cavities are created within this same portion so as to balance out any increase in conductivity due to increased doping with a corresponding increase in resistivity. Increasing the dopant concentration at the semiconductor substrate-insulator layer interface raises the threshold voltage (Vt) of any resulting parasitic capacitors and, thereby reduces harmonic behavior. Also disclosed herein are embodiments of a method for forming such a semiconductor structure.Type: GrantFiled: September 5, 2013Date of Patent: April 29, 2014Assignee: International Business Machines CorporationInventors: Alan B. Botula, John J. Ellis-Monaghan, Alvin J. Joseph, Max G. Levy, Richard A. Phelps, James A. Slinkman, Randy L. Wolf
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Patent number: 8698244Abstract: Disclosed is semiconductor structure with an insulator layer on a semiconductor substrate and a device layer is on the insulator layer. The substrate is doped with a relatively low dose of a dopant having a given conductivity type such that it has a relatively high resistivity. Additionally, a portion of the semiconductor substrate immediately adjacent to the insulator layer can be doped with a slightly higher dose of the same dopant, a different dopant having the same conductivity type or a combination thereof. Optionally, micro-cavities are created within this same portion so as to balance out any increase in conductivity with a corresponding increase in resistivity. Increasing the dopant concentration at the semiconductor substrate-insulator layer interface raises the threshold voltage (Vt) of any resulting parasitic capacitors and, thereby reduces harmonic behavior. Also disclosed herein are embodiments of a method and a design structure for such a semiconductor structure.Type: GrantFiled: December 10, 2009Date of Patent: April 15, 2014Assignee: International Business Machines CorporationInventors: Alan B. Botula, John J. Ellis-Monaghan, Alvin J. Joseph, Max G. Levy, Richard A. Phelps, James A. Slinkman, Randy L. Wolf
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Patent number: 8674472Abstract: A low harmonic radio-frequency (RF) switch in a silicon-on-insulator (SOI) substrate and methods of manufacture. A method includes forming at least one trench through an insulator layer. The at least one trench is adjacent a device formed in an active region on the insulator layer. The method also includes forming at least one cavity in a substrate under the insulator layer and extending laterally from the at least one trench to underneath the device.Type: GrantFiled: August 10, 2010Date of Patent: March 18, 2014Assignee: International Business Machines CorporationInventors: Alan B. Botula, Dinh Dang, James S. Dunn, Alvin J. Joseph, Peter J. Lindgren
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Publication number: 20140004687Abstract: Disclosed is semiconductor structure with an insulator layer on a semiconductor substrate and a device layer is on the insulator layer. The substrate is doped with a relatively low dose of a dopant having a given conductivity type such that it has a relatively high resistivity. Additionally, a portion of the semiconductor substrate immediately adjacent to the insulator layer can be doped with a slightly higher dose of the same dopant, a different dopant having the same conductivity type or a combination thereof. Optionally, micro-cavities are created within this same portion so as to balance out any increase in conductivity due to increased doping with a corresponding increase in resistivity. Increasing the dopant concentration at the semiconductor substrate-insulator layer interface raises the threshold voltage (Vt) of any resulting parasitic capacitors and, thereby reduces harmonic behavior. Also disclosed herein are embodiments of a method for forming such a semiconductor structure.Type: ApplicationFiled: September 5, 2013Publication date: January 2, 2014Applicant: International Business Machines CorporationInventors: Alan B. Botula, John J. Ellis-Monaghan, Alvin J. Joseph, Max G. Levy, Richard A. Phelps, James A. Slinkman, Randy L. Wolf
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Publication number: 20130299903Abstract: A semiconductor device is disclosed. The semiconductor device includes a semiconductor substrate including a first source drain region, a second source drain region, and an intrinsic region therebetween; an asymmetric lightly doped drain (LDD) region within the substrate, wherein the asymmetric LDD region extends from the first source drain region into the intrinsic region between the first source drain region and the second source drain region; and a gate positioned atop the semiconductor substrate, wherein an outer edge of the gate overlaps the second source drain region. A related method and design structure are also disclosed.Type: ApplicationFiled: July 19, 2013Publication date: November 14, 2013Applicant: International Business Machines CorporationInventors: Alan B. Botula, Robert M. Rassel, Yun Shi, Mark E. Stidham
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Patent number: 8564067Abstract: Disclosed is semiconductor structure with an insulator layer on a semiconductor substrate and a device layer is on the insulator layer. The substrate is doped with a relatively low dose of a dopant having a given conductivity type such that it has a relatively high resistivity. Additionally, a portion of the semiconductor substrate immediately adjacent to the insulator layer can be doped with a slightly higher dose of the same dopant, a different dopant having the same conductivity type or a combination thereof. Optionally, micro-cavities are created within this same portion so as to balance out any increase in conductivity due to increased doping with a corresponding increase in resistivity. Increasing the dopant concentration at the semiconductor substrate-insulator layer interface raises the threshold voltage (Vt) of any resulting parasitic capacitors and, thereby reduces harmonic behavior. Also disclosed herein are embodiments of a method for forming such a semiconductor structure.Type: GrantFiled: February 21, 2013Date of Patent: October 22, 2013Assignee: International Business Machines CorporationInventors: Alan B. Botula, John J. Ellis-Monaghan, Alvin J. Joseph, Max G. Levy, Richard A. Phelps, James A. Slinkman, Randy L. Wolf
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Patent number: 8536035Abstract: Silicon-on-insulator (SOI) structures and related methods of forming such structures. In one case, a method includes providing a silicon-on-insulator (SOI) handle substrate having: a substantially uniform resistivity profile along a depth of the handle substrate; and an interstitial oxygen (Oi) concentration of less than approximately 10 parts per million atoms (ppma). The method further includes counter-doping a surface region of the handle, causing the surface region to have a resistivity greater than approximately 3 kOhm-cm, and joining the surface region of the handle substrate with a donor wafer.Type: GrantFiled: February 1, 2012Date of Patent: September 17, 2013Assignee: International Business Machines CorporationInventors: Alan B. Botula, Mark D. Jaffe, Alvin J. Joseph, Kenneth F. McAvey, Gerd Pfeiffer, Richard A. Phelps
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Patent number: 8518782Abstract: A semiconductor device is disclosed. The semiconductor device includes a semiconductor substrate including a first source drain region, a second source drain region, and an intrinsic region therebetween; an asymmetric lightly doped drain (LDD) region within the substrate, wherein the asymmetric LDD region extends from the first source drain region into the intrinsic region between the first source drain region and the second source drain region; and a gate positioned atop the semiconductor substrate, wherein an outer edge of the gate overlaps the second source drain region. A related method and design structure are also disclosed.Type: GrantFiled: December 8, 2010Date of Patent: August 27, 2013Assignee: International Business Machines CorporationInventors: Alan B. Botula, Robert M. Rassel, Yun Shi, Mark E. Stidham