Abstract: A method for manufacturing a semiconductor device comprises forming a plurality of fins in an active region, forming a plurality of gates around the plurality of fins in the active region, forming one or more gate contacts in the active region, and forming a plurality of contacts to source/drain regions in the active region.

Abstract: A method for forming a semiconductor device includes flipping a vertical transistor including a bottom side having at least one connection to at least one bottom side metallization structure, and, after flipping the vertical transistor, forming at least one top side metallization structure having at least one connection to a top side of the vertical transistor.

Abstract: A computer-implemented method of cell placement is provided. The method includes representing a non-rectangular cell to be placed into a cell row and searching the cell row to identify existing objects that are representative of cells in the cell row that are disposable to share space with the non-rectangular cell. The method further includes determining whether a representation of the non-rectangular cell is fittable into a modified mapping of the existing objects in the cell row and, in an event the representation is fittable into the modified mapping, overlapping the representation over one or more of the portions of the existing objects.

Abstract: A method for forming a semiconductor device includes forming bottom side metallization structures having at least one connection to a bottom side of a vertical transistor disposed on a substrate, the bottom side metallization structures including a power rail and a ground rail. After forming the bottom side metallization structures, the substrate is removed and the vertical transistor is flipped. Top side metallization structures are formed. The top side metallization structures having at least one connection to the vertical transistor on a top side of the vertical transistor.

Abstract: A method is presented for forming a layout of a MOSFET (metal oxide semiconductor field effect transistor) circuit. The method includes forming a plurality of gate conductors, forming a plurality of active areas, and forming at least one gate contact (CB contact) within an active region of the plurality of active regions. The method further includes placing a marker over the at least one gate contact to identify a location of the at least one gate contact. Additionally, a distance between the at least one gate contact and at least one TS contact is optimized based on device specifications.

Abstract: A method is presented for forming a layout of a MOSFET (metal oxide semiconductor field effect transistor) circuit. The method includes forming a plurality of gate conductors, forming a plurality of active areas, and forming at least one gate contact (CB contact) within an active region of the plurality of active regions. The method further includes placing a marker over the at least one gate contact to identify a location of the at least one gate contact. Additionally, a distance between the at least one gate contact and at least one TS contact is optimized based on device specifications.

Abstract: A method for manufacturing a semiconductor device comprises forming a plurality of fins in an active region, forming a plurality of gates around the plurality of fins in the active region, forming one or more gate contacts in the active region, and forming a plurality of contacts to source/drain regions in the active region.

Abstract: A technique relates to a method of optimizing self-aligned double patterning. Predefined locations for required metal cuts are provided in order to form metal wires from metal fills that have been cut. Extended locations for extended metal cuts are provided in order to cut adjacent metal fills. The adjacent metal fills are the metal fills that are adjacent to the predefined locations for the required metal cuts, and the extended metal cuts extend beyond the required metal cuts. The required metal cuts into the metal fills are performed and the extended metal cuts into the adjacent metal fills are performed.

Abstract: A method for manufacturing a semiconductor device comprises forming a plurality of fins in an active region, forming a plurality of gates around the plurality of fins in the active region, forming one or more gate contacts in the active region, and forming a plurality of contacts to source/drain regions in the active region.

Abstract: A semiconductor device includes a vertical transistor having a gate structure disposed about a channel region thereof. The vertical transistor has a top side above the gate structure and a bottom side below the gate structure. The top side includes metallization structures having a connection to the vertical transistor on the top side. The bottom side includes metallization structures having a connection to the vertical transistor on the bottom side, and the bottom side includes a power rail and a ground rail.

Abstract: A method for manufacturing a semiconductor device comprises forming a plurality of fins in an active region, forming a plurality of gates around the plurality of fins in the active region, forming one or more gate contacts in the active region, and forming a plurality of contacts to source/drain regions in the active region.

Abstract: A method for forming a semiconductor device includes forming bottom side metallization structures having at least one connection to a bottom side of a vertical transistor disposed on a substrate, the bottom side metallization structures including a power rail and a ground rail. After forming the bottom side metallization structures, the substrate is removed and the vertical transistor is flipped. Top side metallization structures are formed. The top side metallization structures having at least one connection to the vertical transistor on a top side of the vertical transistor.

Abstract: A semiconductor device includes a vertical transistor having a gate structure disposed about a channel region thereof. The vertical transistor has a top side above the gate structure and a bottom side below the gate structure. The top side includes metallization structures having a connection to the vertical transistor on the top side. The bottom side includes metallization structures having a connection to the vertical transistor on the bottom side, and the bottom side includes a power rail and a ground rail.

Abstract: A method is presented for forming a layout of a MOSFET (metal oxide semiconductor field effect transistor) circuit. The method includes forming a plurality of gate conductors, forming a plurality of active areas, and forming at least one gate contact (CB contact) within an active region of the plurality of active regions. The method further includes placing a marker over the at least one gate contact to identify a location of the at least one gate contact. Additionally, a distance between the at least one gate contact and at least one TS contact is optimized based on device specifications.

Abstract: A method is presented for forming a layout of a MOSFET (metal oxide semiconductor field effect transistor) circuit. The method includes forming a plurality of gate conductors, forming a plurality of active areas, and forming at least one gate contact (CB contact) within an active region of the plurality of active regions. The method further includes placing a marker over the at least one gate contact to identify a location of the at least one gate contact. Additionally, a distance between the at least one gate contact and at least one TS contact is optimized based on device specifications.

Abstract: A semiconductor device includes a vertical transistor having a gate structure disposed about a channel region thereof. The vertical transistor has a top side above the gate structure and a bottom side below the gate structure. The top side includes metallization structures having a connection to the vertical transistor on the top side. The bottom side includes metallization structures having a connection to the vertical transistor on the bottom side, and the bottom side includes a power rail and a ground rail.

Abstract: A semiconductor device includes a vertical transistor having a gate structure disposed about a channel region thereof. The vertical transistor has a top side above the gate structure and a bottom side below the gate structure. The top side includes metallization structures having a connection to the vertical transistor on the top side. The bottom side includes metallization structures having a connection to the vertical transistor on the bottom side, and the bottom side includes a power rail and a ground rail.

Abstract: A method for device layout with vertical transistors includes identifying active area regions in a layout of a semiconductor device with vertical transistors. Sets of adjacent active area regions having a same electrical potential are determined. The sets of adjacent active area regions to be merged are prioritized based upon one or more performance criterion. The sets of adjacent active area regions are merged to form larger active area regions according to a priority.

Abstract: A semiconductor device includes a substrate and an active area region forming a bottom source/drain region on the substrate. Vertical transistors are formed on the bottom source/drain region, where the bottom source/drain region is shared between the vertical transistors.

Abstract: Logic circuits, or logic gates, are disclosed comprising vertical transport field effect transistors and one or more active gates, wherein the number of CPP's for the logic circuit, in isolation, is equal to the number of active gates. The components of the logic circuit can be present in at least three different vertical circuit levels, including a circuit level comprising at least one horizontal plane passing through a conductive element that provides an input voltage to the one or more gate structures and another conductive element that provides an output voltage of the logic circuit, and another circuit level that comprises a horizontal plane passing through a conductive bridge from the N output to P output of the field effect transistors. Such logic circuits can include single-gate inverters, two-gate inverters, NOR2 logic gates, and NAND3 logic gates, among other more complicated logic circuits.