Patents by Inventor Alexander Alexeyev
Alexander Alexeyev has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11569806Abstract: Duty cycle adjustment circuitry includes a first stage, a second stage, and decoder circuitry. The first stage includes a first strength tuning circuit having first inverter branches, and a first fine tuning circuit having second inverter branches. The first strength tuning circuit and the first fine tuning circuit are coupled in parallel. The second stage includes a second strength tuning circuit having third inverter branches, and a second fine tuning circuit having fourth inverter branches. The second strength tuning circuit and the second fine tuning circuit are coupled in parallel. Further, the second stage is electrically coupled to the first stage. The decoder circuitry is electrically coupled to the first stage and the second stage. The decoder circuitry controls the first strength tuning circuit independently from the first fine tuning circuit to adjust the duty cycle of an input signal received by the duty cycle adjustment circuitry.Type: GrantFiled: February 2, 2022Date of Patent: January 31, 2023Assignee: Synopsys, Inc.Inventors: Kuan Zhou, David Da-Wei Lin, Vladimir Zlatkovic, Shefali Walia, Youssef Mamdouh El-Toukhy, Abdelrahman Alaa Gouda, Alexander A. Alexeyev
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Publication number: 20220247398Abstract: Duty cycle adjustment circuitry includes a first stage, a second stage, and decoder circuitry. The first stage includes a first strength tuning circuit having first inverter branches, and a first fine tuning circuit having second inverter branches. The first strength tuning circuit and the first fine tuning circuit are coupled in parallel. The second stage includes a second strength tuning circuit having third inverter branches, and a second fine tuning circuit having fourth inverter branches. The second strength tuning circuit and the second fine tuning circuit are coupled in parallel. Further, the second stage is electrically coupled to the first stage. The decoder circuitry is electrically coupled to the first stage and the second stage. The decoder circuitry controls the first strength tuning circuit independently from the first fine tuning circuit to adjust the duty cycle of an input signal received by the duty cycle adjustment circuitry.Type: ApplicationFiled: February 2, 2022Publication date: August 4, 2022Inventors: Kuan ZHOU, David Da-Wei LIN, Vladimir ZLATKOVIC, Shefali WALIA, Youssef Mamdouh EL-TOUKHY, Abdelrahman Alaa GOUDA, Alexander A. ALEXEYEV
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Patent number: 10845440Abstract: Various approaches of adjusting a gain of received signals in integrated circuitry include implementing an open-loop source-degenerated amplifier having a pair of input devices for amplifying the received signals; boosting an effective transconductance of the input devices (e.g., using a pair of super-gm feedback loops); and setting a bias current of devices in the open-loop source-degenerated amplifier (e.g., using a constant-gm bias circuit).Type: GrantFiled: March 26, 2018Date of Patent: November 24, 2020Assignee: WAVEGUIDE CORPORATIONInventors: Michael Trakimas, Alexander Alexeyev
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Patent number: 10794971Abstract: An approach for accurately setting a duty cycle of PA switching waveforms uses an all-digital PVT sensor circuit. In various embodiments, the all-digital PVT sensor circuit measures a pulse width of a periodic reference signal using digital delay line, and subsequently, implements an off-chip digital calculation to program the digital delay line to delay this periodic reference signal so that, when the delayed periodic reference signal is combined with the original (undelayed) reference via a logical AND operation, the resulting signal conforms to a desired duty cycle. In one implementation, the PA is a class-D PA, which may have a single-ended configuration or a differential configuration having two single-ended structures operating in opposite phases.Type: GrantFiled: March 26, 2018Date of Patent: October 6, 2020Assignee: WaveGuide CorporationInventor: Alexander Alexeyev
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Patent number: 10739424Abstract: Systems and methods for reducing variability in the output impedance of an integrated switch-mode power amplifier (PA) split the output impedance between passive resistor, which may be on-chip, and a MOSFET switch of the amplifier. The PA may have a single-ended configuration or a differential configuration having two single-ended structures operating with opposite phases. In one implementation, the size of the MOSFET switch is larger than that of the MOSFET switch implemented in a conventional PA, but the size is still acceptable to operate the PA at a desired frequency. In addition, a calibration approach may be utilized to ensure that the MOSFET switch has a controlled and calibrated ON resistance, thereby providing stable output power levels of the PA and ensuring consistency and repeatability in NMR measurements.Type: GrantFiled: March 26, 2018Date of Patent: August 11, 2020Assignee: WAVEGUIDE CORPORATIONInventor: Alexander Alexeyev
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Patent number: 10551451Abstract: Various approaches of receiving signals in integrated circuitry include implementing two successive stages of signal manipulation and employing an interface having an AC coupling network and buffer circuits for decoupling the output impedance and common-mode level of the first stage of signal manipulation from the input impedance and common-mode level of the second stage of signal manipulation without degrading the performance of either stage.Type: GrantFiled: March 26, 2018Date of Patent: February 4, 2020Assignee: WaveGuide CorporationInventors: Michael Trakimas, Alexander Alexeyev
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Publication number: 20180275231Abstract: Various approaches of receiving signals in integrated circuitry include implementing two successive stages of signal manipulation and employing an interface having an AC coupling network and buffer circuits for decoupling the output impedance and common-mode level of the first stage of signal manipulation from the input impedance and common-mode level of the second stage of signal manipulation without degrading the performance of either stage.Type: ApplicationFiled: March 26, 2018Publication date: September 27, 2018Inventors: Michael TRAKIMAS, Alexander ALEXEYEV
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Publication number: 20180275228Abstract: Systems and methods for reducing variability in the output impedance of an integrated switch-mode power amplifier (PA) split the output impedance between passive resistor, which may be on-chip, and a MOSFET switch of the amplifier. The PA may have a single-ended configuration or a differential configuration having two single-ended structures operating with opposite phases. In one implementation, the size of the MOSFET switch is larger than that of the MOSFET switch implemented in a conventional PA, but the size is still acceptable to operate the PA at a desired frequency. In addition, a calibration approach may be utilized to ensure that the MOSFET switch has a controlled and calibrated ON resistance, thereby providing stable output power levels of the PA and ensuring consistency and repeatability in NMR measurements.Type: ApplicationFiled: March 26, 2018Publication date: September 27, 2018Inventor: Alexander ALEXEYEV
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Publication number: 20180275232Abstract: Various approaches of adjusting a gain of received signals in integrated circuitry include implementing an open-loop source-degenerated amplifier having a pair of input devices for amplifying the received signals; boosting an effective transconductance of the input devices (e.g., using a pair of super-gm feedback loops); and setting a bias current of devices in the open-loop source-degenerated amplifier (e.g., using a constant-gm bias circuit.Type: ApplicationFiled: March 26, 2018Publication date: September 27, 2018Inventors: Michael Trakimas, Alexander Alexeyev
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Publication number: 20180275229Abstract: An approach for accurately setting a duty cycle of PA switching waveforms uses an all-digital PVT sensor circuit. In various embodiments, the all-digital PVT sensor circuit measures a pulse width of a periodic reference signal using digital delay line, and subsequently, implements an off-chip digital calculation to program the digital delay line to delay this periodic reference signal so that, when the delayed periodic reference signal is combined with the original (undelayed) reference via a logical AND operation, the resulting signal conforms to a desired duty cycle. In one implementation, the PA is a class-D PA, which may have a single-ended configuration or a differential configuration having two single-ended structures operating in opposite phases.Type: ApplicationFiled: March 26, 2018Publication date: September 27, 2018Inventor: Alexander ALEXEYEV
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Patent number: 9537492Abstract: An integrated circuit implements at least part of a phase locked loop (PLL). The integrated circuit includes a sampled analog loop filter for the PLL. The loop filter includes a first input for receiving a signal representative of a phase difference between a reference clock signal and a first clock signal, a first output for providing a frequency control signal for controlling a frequency of an oscillator, a clock input for accepting a loop timing clock signal for controlling timing of operation of the loop filter, and a digital control input for configuring a response of the loop filter according to a plurality of control values. In some examples, the loop filter includes charge storage elements coupled by controllable switches, and control circuitry for transferring charge among the charge storage elements to yield the configured response of the loop filter.Type: GrantFiled: June 19, 2015Date of Patent: January 3, 2017Assignee: ANALOG DEVICES, INC.Inventors: Alexander A. Alexeyev, Eric G. Nestler
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Patent number: 9294127Abstract: An analog belief propagation system uses current mode implementations of storage elements and circuit implementations of at least some nodes of a factor graph using current representations. The system mitigates or avoids effects of non-linearities and approximations in storage and processing elements of the system, for instance, by using storage cells that reproduce current values and using factor circuits that separate control sections and signal path sections of the circuits.Type: GrantFiled: September 1, 2011Date of Patent: March 22, 2016Assignee: Analog Devices, Inc.Inventor: Alexander Alexeyev
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Publication number: 20150372682Abstract: An integrated circuit implements at least part of a phase locked loop (PLL). The integrated circuit includes a sampled analog loop filter for the PLL. The loop filter includes a first input for receiving a signal representative of a phase difference between a reference clock signal and a first clock signal, a first output for providing a frequency control signal for controlling a frequency of an oscillator, a clock input for accepting a loop timing clock signal for controlling timing of operation of the loop filter, and a digital control input for configuring a response of the loop filter according to a plurality of control values. In some examples, the loop filter includes charge storage elements coupled by controllable switches, and control circuitry for transferring charge among the charge storage elements to yield the configured response of the loop filter.Type: ApplicationFiled: June 19, 2015Publication date: December 24, 2015Applicant: ANALOG DEVICES, INC.Inventors: ALEXANDER A. ALEXEYEV, ERIC G. NESTLER
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Patent number: 9036420Abstract: A storage device includes a storage array having a group of storage elements. Each storage element can written to a discrete set of physical states. A read circuit selects one or more storage elements and generates, for each selected storage element, an analog signal representative of the physical state of the selected storage element. A signal processing circuit processes the analog signal to generate a plurality of outputs, with each output representing a degree of an association of the selected storage element with a different subset of one or more of the discrete set of physical states.Type: GrantFiled: May 15, 2012Date of Patent: May 19, 2015Assignee: ANALOG DEVICES, INC.Inventors: Benjamin Vigoda, Jeffrey Bernstein, Jeffrey Venuti, Alexander Alexeyev, Eric Nestler, David Reynolds, William Bradley, Vladimir Zlatkovic
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Patent number: 8972831Abstract: A processor includes a first memory module for storing a first set of storage values each representing a respective input, and a second memory module for storing a second set of storage values in analog form. An analog module is coupled to the first and the second memory modules. The analog module is configured to, in each operation cycle of at least one iteration, update at least some of the second set of storage values based on the first and the second sets of storage values. An output module is for generating a set of outputs from at least some of the second set of storage values.Type: GrantFiled: January 11, 2011Date of Patent: March 3, 2015Assignee: Analog Devices, Inc.Inventors: David Reynolds, Benjamin Vigoda, Alexander Alexeyev
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Patent number: 8792602Abstract: A processor implements a network of functional nodes and communication paths between the nodes. The processor includes a plurality of circuit implementations of the functional nodes of the processor; and a plurality of signal paths implementing the communication paths linking the circuit implementations of the nodes. At least some of the signal paths are configured to pass signal values represented according to temporal patterns of signal levels on the signal paths. The processor also includes a plurality of circuit components for conversion between a signal value represented as a signal level (e.g., voltage or current level) and a signal value represented as a temporal pattern.Type: GrantFiled: February 22, 2011Date of Patent: July 29, 2014Assignee: Analog Devices, Inc.Inventors: Jeffrey Bernstein, Benjamin Vigoda, David Reynolds, Alexander Alexeyev, William Bradley
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Patent number: 8572144Abstract: A circuit includes a signal processing circuit for accepting an input and for generating a set of outputs. The input is provided in an input range that has a set of representative values, and each output represents a measure of an association of the input with one or more of the representative values. The signal processing circuit includes a group of output sections, each output section being responsive to the input of the signal processing circuit. Each output section includes one or more sigmoid generators. Each sigmoid generator is responsive to an input of the output section to generate an output that represents a sigmoid function of the input of the output section. Each output section also includes a circuitry for combining the outputs of the one or more sigmoid generators to form one of the set of outputs of the signal processing circuit. An input transformation circuit is coupled to the plurality of output sections.Type: GrantFiled: March 2, 2010Date of Patent: October 29, 2013Assignee: Analog Devices, Inc.Inventors: Benjamin Vigoda, Jeffrey Bernstein, Alexander Alexeyev
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Publication number: 20130219245Abstract: An analog belief propagation system uses current mode implementations of storage elements and circuit implementations of at least some nodes of a factor graph using current representations. The system mitigates or avoids effects of non-linearities and approximations in storage and processing elements of the system, for instance, by using storage cells that reproduce current values and using factor circuits that separate control sections and signal path sections of the circuits.Type: ApplicationFiled: September 1, 2011Publication date: August 22, 2013Applicant: Analog Devices, Inc.Inventor: Alexander Alexeyev
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Publication number: 20130117629Abstract: A processor includes a first memory module for storing a first set of storage values each representing a respective input, and a second memory module for storing a second set of storage values in analog form. An analog module is coupled to the first and the second memory modules. The analog module is configured to, in each operation cycle of at least one iteration, update at least some of the second set of storage values based on the first and the second sets of storage values. An output module is for generating a set of outputs from at least some of the second set of storage values.Type: ApplicationFiled: January 11, 2011Publication date: May 9, 2013Applicant: Analog Devices, Inc.Inventors: David Reynolds, Benjamin Vigoda, Alexander Alexeyev
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Publication number: 20130094298Abstract: A storage device includes a storage array having a group of storage elements. Each storage element can written to a discrete set of physical states. A read circuit selects one or more storage elements and generates, for each selected storage element, an analog signal representative of the physical state of the selected storage element. A signal processing circuit processes the analog signal to generate a plurality of outputs, with each output representing a degree of an association of the selected storage element with a different subset of one or more of the discrete set of physical states.Type: ApplicationFiled: May 15, 2012Publication date: April 18, 2013Applicant: Analog Devices, Inc.Inventors: Benjamin Vigoda, Eric Nestler, Jeffrey Bernstein, David Reynolds, Alexander Alexeyev, Jeffrey Venuti, William Bradley, Vladimir Ziatkovic