Patents by Inventor Alexander Alexeyev
Alexander Alexeyev has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 8344924Abstract: An approach to converting an analog value based on a partition of an input range produces probabilities that the input is found within each of the regions based, for example, on a noisy version of the input. In some examples, iterative and/or pipelined application of comparison circuitry is used to accumulate a set of analog representations of the output probabilities. The circuitry can be adapted or configured according to the characteristics of the degradation (e.g., according to the variance of an additive noise) and/or prior information about the distribution of the clean input (e.g., a distribution over a discrete set of exemplar values, uniformly distributed etc.).Type: GrantFiled: April 27, 2011Date of Patent: January 1, 2013Assignee: Analog Devices, Inc.Inventors: Benjamin Vigoda, Jeffrey Bernstein, Alexander Alexeyev, William Bradley, Theophane Weber
-
Patent number: 8253526Abstract: A system for calibrating operation of integrated differential signal receiver circuitry mounted on a substrate and coupled via surface conductors to edge mounted interface electrodes in which compensation is provided for variances among the resistances of the surface conductors.Type: GrantFiled: July 16, 2007Date of Patent: August 28, 2012Assignee: Texas Instruments IncorporatedInventor: Alexander A. Alexeyev
-
Publication number: 20120194375Abstract: An approach to converting an analog value based on a partition of an input range produces probabilities that the input is found within each of the regions based, for example, on a noisy version of the input. In some examples, iterative and/or pipelined application of comparison circuitry is used to accumulate a set of analog representations of the output probabilities. The circuitry can be adapted or configured according to the characteristics of the degradation (e.g., according to the variance of an additive noise) and/or prior information about the distribution of the clean input (e.g., a distribution over a discrete set of exemplar values, uniformly distributed etc.).Type: ApplicationFiled: April 27, 2011Publication date: August 2, 2012Applicant: Lyric Semiconductor, Inc.Inventors: Benjamin Vigoda, Jeffrey Bernstein, Alexander Alexeyev, William Bradley, Theophane Weber
-
Patent number: 8179731Abstract: A storage device includes a storage array having a group of storage elements. Each storage element can written to a discrete set of physical states. A read circuit selects one or more storage elements and generates, for each selected storage element, an analog signal representative of the physical state of the selected storage element. A signal processing circuit processes the analog signal to generate a plurality of outputs, with each output representing a degree of an association of the selected storage element with a different subset of one or more of the discrete set of physical states.Type: GrantFiled: August 6, 2009Date of Patent: May 15, 2012Assignee: Analog Devices, Inc.Inventors: Benjamin Vigoda, Eric Nestler, Jeffrey Bernstein, David Reynolds, Alexander Alexeyev, Jeffrey Venuti, William Bradley, Vladimir Zlatkovic
-
Patent number: 8107306Abstract: A storage device includes a storage array having a group of storage elements. Each storage element can written to a discrete set of physical states. A read circuit selects one or more storage elements and generates, for each selected storage element, an analog signal representative of the physical state of the selected storage element. A signal processing circuit processes the analog signal to generate a plurality of outputs, with each output representing a degree of an association of the selected storage element with a different subset of one or more of the discrete set of physical states.Type: GrantFiled: August 6, 2009Date of Patent: January 31, 2012Assignee: Analog Devices, Inc.Inventors: Benjamin Vigoda, Eric Nestler, Jeffrey Bernstein, David Reynolds, Alexander Alexeyev, Jeffrey Venuti, William Bradley, Vladimir Zlatkovic
-
Publication number: 20110255612Abstract: A processor implements a network of functional nodes and communication paths between the nodes. The processor includes a plurality of circuit implementations of the functional nodes of the processor; and a plurality of signal paths implementing the communication paths linking the circuit implementations of the nodes. At least some of the signal paths are configured to pass signal values represented according to temporal patterns of signal levels on the signal paths. The processor also includes a plurality of circuit components for conversion between a signal value represented as a signal level (e.g., voltage or current level) and a signal value represented as a temporal pattern.Type: ApplicationFiled: February 22, 2011Publication date: October 20, 2011Applicant: Lyric Semiconductor, Inc.Inventors: Jeffrey Bernstein, Benjamin Vigoda, David Reynolds, Alexander Alexeyev, William Bradley
-
Publication number: 20100281089Abstract: A circuit includes a signal processing circuit for accepting an input and for generating a set of outputs. The input is provided in an input range that has a set of representative values, and each output represents a measure of an association of the input with one or more of the representative values. The signal processing circuit includes a group of output sections, each output section being responsive to the input of the signal processing circuit. Each output section includes one or more sigmoid generators. Each sigmoid generator is responsive to an input of the output section to generate an output that represents a sigmoid function of the input of the output section. Each output section also includes a circuitry for combining the outputs of the one or more sigmoid generators to form one of the set of outputs of the signal processing circuit. An input transformation circuit is coupled to the plurality of output sections.Type: ApplicationFiled: March 2, 2010Publication date: November 4, 2010Applicant: Lyric Semiconductor, Inc.Inventors: Benjamin Vigoda, Jeffrey Bernstein, Alexander Alexeyev, Jeffrey Venuti
-
Publication number: 20100246287Abstract: A storage device includes a storage array having a group of storage elements. Each storage element can written to a discrete set of physical states. A read circuit selects one or more storage elements and generates, for each selected storage element, an analog signal representative of the physical state of the selected storage element. A signal processing circuit processes the analog signal to generate a plurality of outputs, with each output representing a degree of an association of the selected storage element with a different subset of one or more of the discrete set of physical states.Type: ApplicationFiled: August 6, 2009Publication date: September 30, 2010Applicant: Lyric Semiconductor, Inc.Inventors: Benjamin Vigoda, Jeffrey Bernstein, Jeffrey Venuti, David Reynolds, Alexander Alexeyev
-
Publication number: 20100246289Abstract: A storage device includes a storage array having a group of storage elements. Each storage element can written to a discrete set of physical states. A read circuit selects one or more storage elements and generates, for each selected storage element, an analog signal representative of the physical state of the selected storage element. A signal processing circuit processes the analog signal to generate a plurality of outputs, with each output representing a degree of an association of the selected storage element with a different subset of one or more of the discrete set of physical states.Type: ApplicationFiled: August 6, 2009Publication date: September 30, 2010Applicant: Lyric Semiconductor, Inc.Inventors: Benjamin Vigoda, Jeffrey Bernstein, Jeffrey Venuti, David Reynolds, Alexander Alexeyev
-
Publication number: 20100220514Abstract: A storage device includes a storage array having a group of storage elements. Each storage element can written to a discrete set of physical states. A read circuit selects one or more storage elements and generates, for each selected storage element, an analog signal representative of the physical state of the selected storage element. A signal processing circuit processes the analog signal to generate a plurality of outputs, with each output representing a degree of an association of the selected storage element with a different subset of one or more of the discrete set of physical states.Type: ApplicationFiled: August 6, 2009Publication date: September 2, 2010Applicant: Lyric Semiconductor, Inc.Inventors: Benjamin Vigoda, Jeffrey Bernstein, Jeffrey Venuti, Alexander Alexeyev, Eric Nestler, David Reynolds
-
Patent number: 7683673Abstract: Differential signal transmission circuitry in which multiple differential signal transmission circuits are coupled in a stacked relationship between the power supply electrodes to minimize power dissipation by reusing the signal currents among the channels.Type: GrantFiled: May 24, 2007Date of Patent: March 23, 2010Assignee: National Semiconductor CorporationInventors: David J. Fensore, Alexander A. Alexeyev
-
Publication number: 20080278280Abstract: A system for calibrating operation of integrated differential signal receiver circuitry mounted on a substrate and coupled via surface conductors to edge mounted interface electrodes in which compensation is provided for variances among the resistances of the surface conductors.Type: ApplicationFiled: July 16, 2007Publication date: November 13, 2008Applicant: National Semiconductor CorporationInventor: Alexander A. Alexeyev
-
Publication number: 20080266463Abstract: Differential signal transmission circuitry in which multiple differential signal transmission circuits are coupled in a stacked relationship between the power supply electrodes to minimize power dissipation by reusing the signal currents among the channels.Type: ApplicationFiled: May 24, 2007Publication date: October 30, 2008Applicant: National Semiconductor CorporationInventors: David J. Fensore, Alexander A. Alexeyev
-
Patent number: 7355467Abstract: Improvements to the physical layer are provided, for example a test circuit that does not introduce further skew into critical clock signals. A boundary scan test circuit is also provided used to isolate an integrated circuit for applying test vectors or circuit brand connections to test the integrity thereof. A bias voltage generator for a voltage controlled delay line (VCDL) is also provided.Type: GrantFiled: August 14, 2006Date of Patent: April 8, 2008Assignee: Tundra Semiconductor CorporationInventors: Steven M. Waldstein, Maurice Richard, Alexander Alexeyev, David Reynolds
-
Patent number: 7342427Abstract: An apparatus and method for automatically transitioning the operation of an electronic device to a reduced power consumption state if an input reference clock signal is stopped or no longer synchronized (locked) with the operation of the electronic device. The electronic device is automatically returned to a normal operating/power consumption state if the reference clock is restarted. Mixed analog and digital electronic components are employed to handle the transition of the electronic device between reduced and normal power consumption states. These components can include a phase frequency detector and a lost_lock detection circuit. The lost_lock detection circuit is typically connected to the output of phase frequency detector and outputs a lost_lock signal if the reference clock signal has stopped or lost_lock with a feedback clock signal.Type: GrantFiled: December 19, 2005Date of Patent: March 11, 2008Assignee: National Semiconductor CorporationInventors: David James Fensore, Alexander A. Alexeyev
-
Publication number: 20070007995Abstract: Improvements to the physical layer are provided, for example a test circuit that does not introduce further skew into critical clock signals. A boundary scan test circuit is also provided used to isolate an integrated circuit for applying test vectors or circuit brand connections to test the integrity thereof. A bias voltage generator for a voltage controlled delay line (VCDL) is also provided.Type: ApplicationFiled: August 14, 2006Publication date: January 11, 2007Inventors: Steven Waldstein, Maurice Richard, Alexander Alexeyev, David Reynolds
-
Patent number: 7112990Abstract: Improvements to the physical layer are provided, for example a test circuit that does not introduce further skew into critical clock signals. A boundary scan test circuit is also provided used to isolate an integrated circuit for applying test vectors or circuit brand connections to test the integrity thereof. A bias voltage generator for a voltage controlled delay line (VCDL) is also provided.Type: GrantFiled: January 16, 2004Date of Patent: September 26, 2006Assignee: Tundra Semiconductor Corp.Inventors: Steven M. Waldstein, Maurice Richard, Alexander Alexeyev, David Reynolds
-
Publication number: 20050024089Abstract: Improvements to the physical layer are provided, for example a test circuit that does not introduce further skew into critical clock signals. A boundary scan test circuit is also provided used to isolate an integrated circuit for applying test vectors or circuit brand connections to test the integrity thereof. A bias voltage generator for a voltage controlled delay line (VCDL) is also provided.Type: ApplicationFiled: January 16, 2004Publication date: February 3, 2005Inventors: Steven Waldstein, Maurice Richard, Alexander Alexeyev, David Reynolds