Abstract: A gallium nitride (GaN) transistor which includes a multi-layer/multi-thickness barrier layer formed of segments of progressively increasing thickness between the gate and drain to progressively increase the 2DEG density in the channel from gate to drain. The GaN gate can be formed on the base barrier layer to produce an enhancement mode device with a positive threshold voltage. By forming the gate over a thicker segment of the barrier layer, a GaN transistor with a less positive threshold voltage, or a depletion mode transistor with a negative threshold voltage, can be produced.

Abstract: An enhancement mode gallium nitride (GaN) transistor with a p-type gate configured to eliminate holes accumulating under the gate metal. The gate has two electrodes, a gate electrode and a hole collector electrode. In a preferred embodiment, a negative voltage is applied to the hole collector electrode, attracting holes accumulating under the gate metal. The attracted holes recombine with electrons supplied by the negative voltage, thereby substantially eliminating the holes.

Abstract: An enhancement mode GaN transistor that includes a multi-region field plate which partially overlaps the gate and partially overlaps a barrier offset layer. The multi-region field plate includes a section of increased height with respect to the channel layer over the portion of the gate nearest the drain contact, and a section of reduced height with respect to the channel layer over the edge or transition of the barrier offset layer, minimizing the peak electric field at the corner of the gate and at the edge or transition of the barrier offset layer.

Abstract: An integrated circuit that includes a plurality of GaN transistor sets. A first set of the plurality of GaN transistor sets includes transistors with a first drain-to-source distance, and wherein a second of the plurality of GaN transistor sets includes transistors with a second drain-to-source distance that is greater than the first drain-to-source distance.

Abstract: An integrated circuit that includes a plurality of GaN transistor sets. A first set of the plurality of GaN transistor sets includes transistors with a first drain-to-source distance, and wherein a second of the plurality of GaN transistor sets includes transistors with a second drain-to-source distance that is greater than the first drain-to-source distance.

Abstract: Circuits, structures and techniques for independently connecting a surrounding material in a part of a semiconductor device to a contact of its respective device. To achieve this, a combination of one or more conductive wells that are electrically isolated in at least one bias polarity are provided.

Abstract: An integrated DC-DC converter device includes a plurality of GaN transistor sets. A first set of the plurality of GaN transistor sets includes transistors with a first drain-to-source distance, and wherein a second of the plurality of GaN transistor sets includes transistors with a second drain-to-source distance that is greater than the first drain-to-source distance.

Abstract: Circuits, structures and techniques for independently connecting a surrounding material in a part of a semiconductor device to a contact of its respective device. To achieve this, a combination of one or more conductive wells that are electrically isolated in at least one bias polarity are provided.

Abstract: An enhancement-mode GaN transistor with reduced gate leakage current between a gate contact and a 2DEG region and a method for manufacturing the same. The enhancement-mode GaN transistor including a GaN layer, a barrier layer disposed on the GaN layer with a 2DEG region formed at an interface between the GaN layer and the barrier layer, and source contact and drain contacts disposed on the barrier layer. The GaN transistor further includes a p-type gate material formed above the barrier layer and between the source and drain contacts and a gate metal disposed on the p-type gate material, with wherein the p-type gate material including comprises a pair of self-aligned ledges that extend toward the source contact and drain contact, respectively.

Abstract: Circuits, structures and techniques for independently connecting a surrounding material in a part of a semiconductor device to a contact of its respective device. To achieve this, a combination of one or more conductive wells that are electrically isolated in at least one bias polarity are provided.

Abstract: A GaN transistor with polysilicon layers for creating additional components for an integrated circuit and a method for manufacturing the same. The GaN device includes an EPI structure and an insulating material disposed over EPI structure. Furthermore, one or more polysilicon layers are disposed in the insulating material with the polysilicon layers having one or more n-type regions and p-type regions. The device further includes metal interconnects disposed on the insulating material and vias disposed in the insulating material layer that connect source and drain metals to the n-type and p-type regions of the polysilicon layer.

Abstract: An integrated DC-DC converter device includes a plurality of GaN transistor sets. A first set of the plurality of GaN transistor sets includes transistors with a first drain-to-source distance, and wherein a second of the plurality of GaN transistor sets includes transistors with a second drain-to-source distance that is greater than the first drain-to-source distance.

Abstract: A GaN transistor with polysilicon layers for creating additional components for an integrated circuit and a method for manufacturing the same. The GaN device includes an EPI structure and an insulating material disposed over EPI structure. Furthermore, one or more polysilicon layers are disposed in the insulating material with the polysilicon layers having one or more n-type regions and p-type regions. The device further includes metal interconnects disposed on the insulating material and vias disposed in the insulating material layer that connect source and drain metals to the n-type and p-type regions of the polysilicon layer.

Abstract: A GaN transistor with polysilicon layers for creating additional components for an integrated circuit and a method for manufacturing the same. The GaN device includes an EPI structure and an insulating material disposed over EPI structure. Furthermore, one or more polysilicon layers are disposed in the insulating material with the polysilicon layers having one or more n-type regions and p-type regions. The device further includes metal interconnects disposed on the insulating material and vias disposed in the insulating material layer that connect source and drain metals to the n-type and p-type regions of the polysilicon layer.

Abstract: An enhancement-mode GaN transistor with reduced gate leakage current between a gate contact and a 2DEG region and a method for manufacturing the same. The enhancement-mode GaN transistor including a GaN layer, a barrier layer disposed on the GaN layer with a 2DEG region formed at an interface between the GaN layer and the barrier layer, and source contact and drain contacts disposed on the barrier layer. The GaN transistor further includes a p-type gate material formed above the barrier layer and between the source and drain contacts and a gate metal disposed on the p-type gate material, with wherein the p-type gate material including comprises a pair of self-aligned ledges that extend toward the source contact and drain contact, respectively.

Abstract: An enhancement-mode GaN transistor with reduced gate leakage current between a gate contact and a 2DEG region and a method for manufacturing the same. The enhancement-mode GaN transistor including a GaN layer, a barrier layer disposed on the GaN layer with a 2DEG region formed at an interface between the GaN layer and the barrier layer, and source contact and drain contacts disposed on the barrier layer. The GaN transistor further includes a p-type gate material formed above the barrier layer and between the source and drain contacts and a gate metal disposed on the p-type gate material, with wherein the p-type gate material including comprises a pair of self- aligned ledges that extend toward the source contact and drain contact, respectively.

Abstract: Circuits, structures and techniques for independently connecting a surrounding material in a part of a semiconductor device to a contact of its respective device. To achieve this, a combination of one or more conductive wells that are electrically isolated in at least one bias polarity are provided.

Abstract: Circuits, structures and techniques for independently connecting a surrounding material in a part of a semiconductor device to a contact of its respective device. To achieve this, a combination of one or more conductive wells that are electrically isolated in at least one bias polarity are provided.

Abstract: An integrated circuit having a substrate, a buffer layer formed over the substrate, a barrier layer formed over the buffer layer, and an isolation region that isolates an enhancement mode device from a depletion mode device. The integrated circuit further includes a first gate contact for the enhancement mode device that is disposed in one gate contact recess and a second gate contact for the depletion mode device that is disposed in a second gate contact recess.

Abstract: An enhancement-mode GaN transistor with reduced gate leakage current between a gate contact and a 2DEG region and a method for manufacturing the same. The enhancement-mode GaN transistor including a GaN layer, a barrier layer disposed on the GaN layer with a 2DEG region formed at an interface between the GaN layer and the barrier layer, and source contact and drain contacts disposed on the barrier layer. The GaN transistor further includes a p-type gate material formed above the barrier layer and between the source and drain contacts and a gate metal disposed on the p-type gate material, with wherein the p-type gate material including comprises a pair of self-aligned ledges that extend toward the source contact and drain contact, respectively.