Abstract: The gate electrode pad and the source electrode pad of a high power MOSFET are supported atop an oxide layer. The peripheral regions of the source electrode which surround the areas of the gate and source pads are connected at a plurality of points around their peripheries through the oxide layer to the underlying silicon. This enables rapid collection of minority carriers which were weakly injected into the region surrounding the pads when a junction beneath the pads is forward-biased.

Abstract: A high power MOSFET is disclosed in which two laterally spaced sources each supply current through respective channels in one surface of a semiconductor chip which are controlled by the same gate. The channels lead from the source electrodes to a relatively low resistivity region and from there to a relatively high resistivity epitaxially formed region which is deposited on a high conductivity substrate. The drain electrode may be either on the opposite surface of the chip or laterally displaced from and on the same side as the source regions. The epitaxially deposited semiconductor material immediately adjacent and beneath the gate and in the path from the sources to the drain has a relatively high conductivity, thereby to substantially reduce the on-resistance of the device without effecting the breakdown voltage of the device.

Abstract: A high power MOSFET structure consists of a plurality of source cells distributed over the upper surface of a semiconductor chip, with a drain electrode on the bottom of the chip. Each of the source cells is hexagonal in configuration and is surrounded by a narrow, hexagonal conduction region disposed beneath a gate oxide. The semiconductor material beneath the gate oxide has a relatively high conductivity, with the carriers being laterally equally distributed in density beneath the gate oxide. The high conductivity hexagonal channel is formed in a low conductivity epitaxially formed region and consists of carriers deposited on the epitaxial region prior to the formation of the source region. Symmetrically arranged gate fingers extend over the upper surface of the device and extend through and along slits in the upper source metallizing and are connected to a polysilicon gate grid which overlies the gate oxide.

Abstract: A high power MOSFET is disclosed in which two laterally spaced sources each supply current through respective channels in one surface of a semiconductor chip which are controlled by the same gate. The channels lead from the source electrodes to a relatively low resistivity region and from there to a relatively high resistivity epitaxially formed region which is deposited on a high conductivity substrate. The drain electrode may be either on the opposite surface of the chip or laterally displaced from and on the same side as the source regions. The epitaxially deposited semiconductor material immediately adjacent and beneath the gate and in the path from the sources to the drain has a relatively high conductivity, thereby to substantially reduce the on-resistance of the device without effecting the breakdown voltage of the device.

Abstract: A high power MOSFET structure consists of a plurality of source cells distributed over the upper surface of a semiconductor chip, with a drain electrode on the bottom of the chip. Each of the source cells is hexagonal in configuration and is surrounded by a narrow, hexagonal conduction region disposed beneath a gate oxide. The semiconductor material beneath the gate oxide has a relatively high conductivity, with the carriers being laterally equally distributed in density beneath the gate oxide. The high conductivity hexagonal channel is formed in a low conductivity epitaxially formed region and consists of carriers deposited on the epitaxial region prior to the formation of the source region. Symmetrically arranged gate fingers extend over the upper surface of the device and extend through and along slits in the upper source metallizing and are connected to a polysilicon gate grid which overlies the gate oxide.

Abstract: A high speed, high power bipolar transistor has a planar emitter structure having a central area and outer peripheral areas. The doping concentration in the central area is reduced as compared to that of the outer areas to reduce the injection efficiency at the central area of the emitter region. A low doped region of conductivity type opposite to that of the emitter surrounds the emitter area and can fully deplete to spread out the field to permit high voltage breakdown for the device. A novel process of manufacture is used wherein the doping concentration across the emitter area is controlled by diffusing the emitter through a pattern of elongated or rectangular or other cross-section masking islands which have closer spacing in the center of the emitter region to produce a lower average doping concentration in the center of the emitter than in the outer peripheral regions of the emitter.

Abstract: Two gaps are placed in the reflowed phosphorus-doped silicon dioxide material overcoating of a planar high voltage semiconductor device to prevent polarization of the reflowed silox. The invention is applicable to any device using a polarizable glassy coating which will be exposed to a high electric field extending along its surface and is shown applied to a high voltage diode, a high voltage MOSFET and a high voltage TRIMOS-type device which is a semiconductor switching device using spaced MOS transistors having a common drain region.

Abstract: A field plate structure is provided to terminate the electrode of a semiconductor device in a manner to reduce curvature of electric field within the body of the semiconductor device underlying the electrode and surrounding the electrode. A stepped electrode outer rim is provided in effect through the use of an underlying polysilicon which drapes over an underlying oxide. The main contact metal, typically aluminum, overlies the polysilicon but is upwardly displaced above the relatively thin polysilicon by a relatively thick oxide layer over the polysilicon. The composite effect of the thin polysilicon layer at one level and the heavier metallizing at a higher level but overlapping the polysilicon is that of a metal electrode deposited atop an insulation layer having two steps therein.

Abstract: A high power MOSFET is disclosed in which two laterally spaced sources each supply current through respective channels in one surface of a semiconductor chip which are controlled by the same gate. The channels lead from the source electrodes to a relatively low resistivity region and from there to a relatively high resistivity epitaxially formed region which is deposited on a high conductivity substrate. The drain electrode may be either on the opposite surface of the chip or laterally displaced from and on the same side as the source regions. The epitaxially deposited semiconductor material immediately adjacent and beneath the gate and in the path from the sources to the drain has a relatively high conductivity, thereby to substantially reduce the on-resistance of the device without affecting the breakdown voltage of the device.