Abstract: A method includes aligning and positioning a carrier in a predetermined orientation and location within a first front opening pod (FOUP) of a cluster tool, transferring the carrier to a charging station of the cluster tool, transferring a substrate from a second front opening pod (FOUP) of the cluster tool to the charging station and chucking the substrate onto the carrier, transferring the carrier having the substrate thereon from the charging station to a factory interface of the cluster tool, aligning the carrier having the substrate thereon in the factory interface of the cluster tool such that during substrate processing within a processing platform of the cluster tool the carrier is properly oriented and positioned relative to components of the processing platform, where the processing platform comprises one or more processing chambers, transferring the aligned carrier having the substrate thereon from the factory interface to the processing platform of the cluster tool for substrate processing, and tra

Abstract: A chucking station comprises a chuck, a power supply, and one or more pumping elements. The chuck comprises a plurality of first vacuum ports configured to interface with a surface of a substrate and a plurality of second vacuum ports configured to interface with a surface of a carrier. The chuck further comprises a first electrical pin configured to be in electrical communication with a first electrode of the carrier, and a second electrical pin configured to be in electrical communication with a second electrode of the carrier. The power supply is configured to apply a chucking voltage and a de-chucking voltage to the first and second electrical pins. The one or more pumping elements is coupled to the first and second vacuum ports and configured to generate a vacuum between the substrate and the chuck and a vacuum between the carrier and the chuck.

Abstract: One or more embodiments described herein generally relate to methods and systems for forming films on substrates in semiconductor processes. In embodiments described herein, process chamber is provided that includes a lid plate having a plurality of cooling channels formed therein, a pedestal, the pedestal having a plurality of cooling channels formed therein, and a showerhead, wherein the showerhead comprises a plurality of segments and each segment is at least partially surrounded by a shield.

Abstract: Embodiments of the present disclosure generally relate to a processing system for forming one or more layers of a photodiode. In one embodiment, the processing system includes a transfer chamber, a plurality of processing chambers, and a controller configured to cause a process to be performed in the processing system. The process includes performing a pre-clean process on a substrate, aligning and placing a first mask on the substrate, depositing a first layer on the substrate, and depositing a second layer on the substrate. The processing system can form layers of a photodiode in a low defect, cost effective, and high utilization manner.

Abstract: One or more embodiments described herein generally relate to methods and systems for forming films on substrates in semiconductor processes. In embodiments described herein, a process system includes different materials each contained in separate ampoules. Each material is flowed into a separate portion of a showerhead contained within a process chamber via a heated gas line. From the showerhead, each material is flowed on to a substrate that sits on the surface of a rotating pedestal. Controlling the mass flow rate out of the showerhead and the rotation rate of the pedestal helps result in films with desirable material domain sizes to be deposited on the substrate.

Abstract: An alignment module for positioning a mask on a substrate comprises a mask stocker, an alignment stage, and a transfer robot. The mask stocker houses a mask cassette that stores a plurality of masks. The alignment stage is configured to support a carrier and a substrate. The transfer robot is configured to transfer one of the one or more masks from the mask stocker to the alignment stage and position the mask over the substrate. The alignment module may be part of an integrated platform having one or more transfer chambers, a factory interface having a substrate carrier chamber and one or more processing chambers. A carrier may be coupled to a substrate within the substrate carrier chamber and moved between the processing chambers to generate a semiconductor device.

Abstract: An alignment module for housing and cleaning masks. The alignment module comprises a mask stocker, a cleaning chamber, an alignment chamber, an alignment stage a transfer robot. The mask stocker is configured to house a mask cassette configured to store a plurality of masks. The cleaning chamber is configured to clean the plurality of masks by providing one or more cleaning gases into a chamber after a mask is inserted into the cleaning chamber. The alignment stage is configured to support a carrier and a substrate. The transfer robot is configured to transfer a mask from one or more of the alignment stage and the mask stocker to the cleaning chamber.

Abstract: Methods and apparatuses for aligning masks with substrates are provided. A method can include receiving a carrier having a substrate disposed thereon at an alignment stage of an alignment module, transferring a mask from a mask cassette of a mask stocker of the alignment module to a position over the alignment stage, and positioning the mask on the carrier. The method can also include acquiring one or more images of the mask and the substrate, where the mask contains one or more alignment holes passing through the mask and the substrate contains one or more alignment dots disposed on an upper surface of the substrate, analyzing the one or more images to determine one or more differences between one or more alignment holes of the mask and one or more alignment dots on the substrate, and aligning the mask with the substrate based on the differences.

Abstract: Generally, examples described herein relate to deposition masks and methods of manufacturing and using such deposition masks. An example includes a method for forming a deposition mask. A mask layer is deposited on a substrate. Mask openings are patterned through the mask layer. A central portion of the substrate is removed to define a substrate opening through a periphery portion of the substrate. The mask layer with the mask openings through the mask layer extending across the substrate opening.

Abstract: Methods of and apparatuses for dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a plasma etch apparatus includes a plasma etch chamber. The plasma etch chamber includes a plasma source disposed in an upper region of the plasma etch chamber, a cathode assembly disposed below the plasma source, and a support pedestal for supporting a substrate carrier below the plasma source. The plasma etch apparatus also includes a transfer chamber coupled to the plasma etch chamber. The transfer chamber includes a transfer arm for supporting a substantial portion of a dicing tape of the substrate carrier, the transfer arm configured to transfer a sample from the support pedestal following an etch singulation process.

Abstract: Methods of and apparatuses for dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a plasma etch apparatus includes a plasma etch chamber. The plasma etch chamber includes a plasma source disposed in an upper region of the plasma etch chamber, a cathode assembly disposed below the plasma source, and a support pedestal for supporting a substrate carrier below the plasma source. The plasma etch apparatus also includes a transfer chamber coupled to the plasma etch chamber. The transfer chamber includes a transfer arm for supporting a substantial portion of a dicing tape of the substrate carrier, the transfer arm configured to transfer a sample from the support pedestal following an etch singulation process.

Abstract: Light-absorbing masks and methods of dicing semiconductor wafers are described. In an example, a method of dicing a semiconductor wafer including a plurality of integrated circuits involves forming a mask above the semiconductor wafer. The mask includes a water-soluble matrix based on a solid component and water, and a light-absorber species throughout the water-soluble matrix. The mask and a portion of the semiconductor wafer are patterned with a laser scribing process to provide a patterned mask with gaps and corresponding trenches in the semiconductor wafer in regions between the integrated circuits. The semiconductor wafer is plasma etched through the gaps in the patterned mask to extend the trenches and to singulate the integrated circuits. The patterned mask protects the integrated circuits during the plasma etching.

Abstract: Etch masks and methods of dicing semiconductor wafers are described. In an example, an etch mask for a wafer singulation process includes a water-soluble matrix based on a solid component and water. The etch mask also includes a plurality of particles dispersed throughout the water-soluble matrix. The plurality of particles has an average diameter approximately in the range of 5-100 nanometers. A ratio of weight % of the solid component to weight % of the plurality of particles is approximately in the range of 1:0.1-1:4.

Abstract: Methods and apparatus for rapid thermal processing of a planar substrate including axially aligning the substrate with a substrate support or with an empirically determined position are described. The methods and apparatus include a sensor system that determines the relative orientations of the substrate and the substrate support.

Abstract: Methods of and apparatuses for dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a shadow ring assembly for a plasma processing chamber includes an annular body including a thermally conductive material. The annular body includes a top surface to face an interior of the plasma chamber, and a bottom surface to face a substrate carrier in the plasma chamber. A plurality of posts are attached to the annular body and positioned substantially below the bottom surface of the annular body. Each of the plurality of posts includes an inner core of thermal pyrolytic graphite (TPG). The shadow ring assembly also includes a plasma resistant coating on the annular body and the plurality of posts.

Abstract: The present invention generally relates to methods and apparatus for processing substrates. Embodiments of the invention include apparatuses for processing a substrate comprising a ceramic reflector plate, which may be optically transparent. The reflector plate may include a reflective coating and be part of a reflector plate assembly in which the reflector plate is assembled to a baseplate.

Abstract: Methods and apparatus for rapid thermal processing of a planar substrate including axially aligning the substrate with a substrate support or with an empirically determined position are described. The methods and apparatus include a sensor system that determines the relative orientations of the substrate and the substrate support.

Abstract: Methods of and apparatuses for dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a plasma etch apparatus includes a plasma etch chamber. The plasma etch chamber includes a plasma source disposed in an upper region of the plasma etch chamber, a cathode assembly disposed below the plasma source, and a support pedestal for supporting a substrate carrier below the plasma source. The plasma etch apparatus also includes a transfer chamber coupled to the plasma etch chamber. The transfer chamber includes a transfer arm for supporting a substantial portion of a dicing tape of the substrate carrier, the transfer arm configured to transfer a sample from the support pedestal following an etch singulation process.

Abstract: Methods of and carriers for dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a cover ring for protecting a carrier and substrate assembly during an etch process includes an inner opening having a diameter smaller than the diameter of a substrate of the carrier and substrate assembly. An outer frame surrounds the inner opening. The outer frame has a bevel for accommodating an outermost portion of the substrate of the carrier and substrate assembly.

Abstract: In one embodiment, a substrate processing apparatus includes a chamber having an interior volume with an upper portion and a lower portion, a cooling source disposed in the upper portion of the interior volume, a heating source opposing the cooling source, a magnetically movable substrate support that moves between the upper portion and the lower the portion, and a plurality of sensors coupled to the chamber to detect the position of the substrate support relative to the heating source and the cooling source.