Patents by Inventor Alexis Farcy
Alexis Farcy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220045020Abstract: A method for fabricating a semiconductor chip includes forming a plurality of conducting pads at a front face of a substrate, thinning a rear face of the substrate, etching openings under each conducting pad from the rear face, depositing a layer of a dielectric on walls and a bottom of the openings, forming a conducting material in the openings, and forming a conducting strip on the rear face. The conducting strip is electrically connected to the conducting material of each of the openings. The etching is stopped when the respective conducting pad is reached.Type: ApplicationFiled: October 21, 2021Publication date: February 10, 2022Inventors: Sebastien Petitdidier, Nicolas Hotellier, Raul Andres Bianchi, Alexis Farcy, Benoit Froment
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Patent number: 11183468Abstract: A semiconductor chip includes at least two insulated vias passing through the chip from the front face to the rear face in which, on the side of the rear face, the vias are connected to one and the same conducting strip and, on the side of the front face, each via is separated from a conducting pad by a layer of a dielectric.Type: GrantFiled: June 30, 2017Date of Patent: November 23, 2021Assignee: STMICROELECTRONICS (CROLLES 2) SASInventors: Sebastien Petitdidier, Nicolas Hotellier, Raul Andres Bianchi, Alexis Farcy, Benoît Froment
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Publication number: 20180061781Abstract: A semiconductor chip includes at least two insulated vias passing through the chip from the front face to the rear face in which, on the side of the rear face, the vias are connected to one and the same conducting strip and, on the side of the front face, each via is separated from a conducting pad by a layer of a dielectric.Type: ApplicationFiled: June 30, 2017Publication date: March 1, 2018Inventors: Sebastien Petitdidier, Nicolas Hotellier, Raul Andres Bianchi, Alexis Farcy, Benoît Froment
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Patent number: 8841748Abstract: A dielectric wafer has, on top of its front face, a front electrical connection including an electrical connection portion. A blind hole passes through from a rear face of the wafer to at least partially reveal a rear face of the electrical connection portion. A through capacitor is formed in the blind hole. The capacitor includes a first conductive layer covering the lateral wall and the electrical connection portion (forming an outer electrode), a dielectric intermediate layer covering the first conductive layer (forming a dielectric membrane), and a second conductive layer covering the dielectric intermediate layer (forming an inner electrode). A rear electrical connection is made to the inner electrode.Type: GrantFiled: November 17, 2011Date of Patent: September 23, 2014Assignee: STMicroelectronics SAInventors: Sylvain Joblot, Alexis Farcy, Jean-Francois Carpentier, Pierre Bar
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Patent number: 8766381Abstract: The integrated circuit comprises a support substrate having opposite first and second main surfaces. A cavity passes through the support substrate and connects the first and second main surfaces. The integrated circuit comprises a device with a mobile element, the mobile element and a pair of associated electrodes of which are included in a cavity. An anchoring node of the mobile element is located at the level of the first main surface. The integrated circuit comprises a first elementary chip arranged at the level of the first main surface and electrically connected to the device with a mobile element.Type: GrantFiled: September 12, 2011Date of Patent: July 1, 2014Assignees: STMicroelectronics SA, STMicroelectronics (Crolles 2) SASInventors: Fabrice Casset, Lionel Cadix, Perceval Coudrain, Alexis Farcy, Laurent-Luc Chapelon, Yacine Felk, Pascal Ancey
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Patent number: 8704363Abstract: An interface plate capable of being mounted between first and second surface-mounted electronic chips. The plate includes a plurality of first, second, and third through openings, the first openings being filled with a conductive material and being arranged to be in front of pads of the first and second chips during the assembly, the second openings being filled with a second material, the third openings being filled with a third material, the second and third materials forming two complementary components of a thermoelectric couple.Type: GrantFiled: October 22, 2010Date of Patent: April 22, 2014Assignee: STMicroelectronics S.A.Inventors: Yacine Felk, Alexis Farcy
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Publication number: 20130286540Abstract: A method of forming a metal- insulator-metal capacitor having top and bottom plates separated by a dielectric layer, one of the top and bottom plates having at least one protrusion extending into a corresponding cavity in the other of the top and bottom plates, the method including the steps of growing one or more nanofibers on a base surface.Type: ApplicationFiled: March 14, 2013Publication date: October 31, 2013Inventors: Alexis Farcy, Maryline Thomas, Joaquin Torres, Sonarith Chhun, Laurent-Georges Gosset
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Patent number: 8424177Abstract: A method of forming a metal-insulator-metal capacitor having top and bottom plates separated by a dielectric layer, one of the top and bottom plates having at least one protrusion extending into a corresponding cavity in the other of the top and bottom plates, the method including the steps of growing one or more nanofibers on a base surface.Type: GrantFiled: May 6, 2010Date of Patent: April 23, 2013Assignees: STMicroelectronics (Crolles 2) SAS, NXP B.V. (Dutch Corporation)Inventors: Alexis Farcy, Maryline Thomas, Joaquin Torres, Sonarith Chhun, Laurent-Georges Gosset
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Patent number: 8410574Abstract: An integrated microelectronic device is formed from a substrate having a first side and a second side and including a doped active zone (2) in the first side of the substrate. A circuit component is situated in the doped active zone. A through silicon via extends between the second side and the first side, the via being electrically isolated from the substrate by an insulating layer. A buffer zone is situated between the insulating layer and the doped active zone. This buffer zone is positioned under a shallow trench isolation zone provided around the doped active zone. The buffer zone functions to reduce the electrical coupling between the through silicon via and the doped active zone.Type: GrantFiled: December 7, 2010Date of Patent: April 2, 2013Assignee: STMicroelectronics (Crolles 2) SASInventors: Alexis Farcy, Maxime Rousseau
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Publication number: 20120133020Abstract: A dielectric wafer has, on top of its front face, a front electrical connection including an electrical connection portion. A blind hole passes through from a rear face of the wafer to at least partially reveal a rear face of the electrical connection portion. A through capacitor is formed in the blind hole. The capacitor includes a first conductive layer covering the lateral wall and the electrical connection portion (forming an outer electrode), a dielectric intermediate layer covering the first conductive layer (forming a dielectric membrane), and a second conductive layer covering the dielectric intermediate layer (forming an inner electrode). A rear electrical connection is made to the inner electrode.Type: ApplicationFiled: November 17, 2011Publication date: May 31, 2012Applicant: STMICROELECTRONICS S.A.Inventors: Sylvain Joblot, Alexis Farcy, Jean-Francois Carpentier, Pierre Bar
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Publication number: 20120074527Abstract: The integrated circuit comprises a support substrate having opposite first and second main surfaces. A cavity passes through the support substrate and connects the first and second main surfaces. The integrated circuit comprises a device with a mobile element, the mobile element and a pair of associated electrodes of which are included in a cavity. An anchoring node of the mobile element is located at the level of the first main surface. The integrated circuit comprises a first elementary chip arranged at the level of the first main surface and electrically connected to the device with a mobile element.Type: ApplicationFiled: September 12, 2011Publication date: March 29, 2012Applicants: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, STMICROELECTRONICS (CROLLES 2) SAS, STMICROELECTRONICS SAInventors: Fabrice Casset, Lionel Cadix, Perceval Coudrain, Alexis Farcy, Laúrent-Lüc Chapelon, Yacine Felk, Pascal Ancey
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Publication number: 20110140231Abstract: An integrated microelectronic device is formed from a substrate having a first side and a second side and including a doped active zone (2) in the first side of the substrate. A circuit component is situated in the doped active zone. A through silicon via extends between the second side and the first side, the via being electrically isolated from the substrate by an insulating layer. A buffer zone is situated between the insulating layer and the doped active zone. This buffer zone is positioned under a shallow trench isolation zone provided around the doped active zone. The buffer zone functions to reduce the electrical coupling between the through silicon via and the doped active zone.Type: ApplicationFiled: December 7, 2010Publication date: June 16, 2011Applicant: STMICROELECTRONICS (CROLLES 2) SASInventors: Alexis Farcy, Maxime Rousseau
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Publication number: 20110095437Abstract: An interface plate capable of being mounted between first and second surface-mounted electronic chips. The plate includes a plurality of first, second, and third through openings, the first openings being filled with a conductive material and being arranged to be in front of pads of the first and second chips during the assembly, the second openings being filled with a second material, the third openings being filled with a third material, the second and third materials forming two complementary components of a thermoelectric couple.Type: ApplicationFiled: October 22, 2010Publication date: April 28, 2011Applicant: STMicroelectronics S.A.Inventors: Yacine Felk, Alexis Farcy
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Publication number: 20110086468Abstract: A method for assembling a first semiconductor chip provided with pads on a second semiconductor chip or wafer provided with pads, comprising covering the chip(s) with a dielectric, superposing the two chips, the pads being arranged substantially opposite to each other, and applying a voltage difference between the pads of the first and second chips to cause a breakdown of the dielectric and a diffusion of the conductor forming the pads into the broken down areas, whereby a conductive path forms between the opposite pads.Type: ApplicationFiled: October 5, 2010Publication date: April 14, 2011Inventors: Yacine Felk, Hamed Chaabouni, Alexis Farcy
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Publication number: 20110080686Abstract: A method of forming a metal-insulator-metal capacitor having top and bottom plates separated by a dielectric layer, one of the top and bottom plates having at least one protrusion extending into a corresponding cavity in the other of the top and bottom plates, the method including the steps of growing one or more nanofibers on a base surface.Type: ApplicationFiled: May 6, 2010Publication date: April 7, 2011Applicants: STMicroelectronics (Crolles 2) SAS, NXP B.V. (Dutch Corporation)Inventors: Alexis Farcy, Maryline Thomas, Joaquin Torres, Sonarith Chhun, Laurent-Georges Gosset
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Publication number: 20070096253Abstract: A capacitor incorporated into an integrated electronic circuit comprises two plates and a series of intermediate layers placed between the plates. The intermediate layers are alternately insulating layers and conducting layers, and each conducting layer is electrically isolated from the rest of the circuit. Such a capacitor may have a high breakdown voltage.Type: ApplicationFiled: May 17, 2006Publication date: May 3, 2007Applicant: STMicroelectronics (Crolles 2) SASInventors: Joaquin Torres, Alexis Farcy
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Publication number: 20070063240Abstract: An integrated electronic circuit includes electrical connections located in metallization layers superposed on top of a substrate. The circuit further incorporates a capacitor having two plates that are placed in two adjacent metallization layers. Each of the metallization layers containing a capacitor plate further contains electrical connections. The capacitor is compatible with a high level of integration of the circuit and may be produced using the damascene process.Type: ApplicationFiled: September 7, 2006Publication date: March 22, 2007Applicant: STMicroelectronics (Crolles 2) SASInventors: Joaquin Torres, Alexis Farcy
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Patent number: 6949444Abstract: A method for forming at least one conductive line intended to receive high-frequency or high-value currents, formed above a given portion of a solid substrate outside of which are formed other elements, including the steps of digging at least one trench in the solid substrate; forming an insulating area in the trench; and forming said conductive line above the insulating area.Type: GrantFiled: April 5, 2002Date of Patent: September 27, 2005Assignee: STMicroelectronics S.A.Inventors: Joaquim Torres, Vincent Arnal, Alexis Farcy
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Patent number: 6846690Abstract: The fabrication of an integrated circuit includes a first phase of producing an electronic chip and a second phase of producing at least one auxiliary component placed above the chip and of producing a protective cover which covers the auxiliary component. The first phase of producing the chip is effected from a first semiconductor substrate and comprises the formation of a cavity lying in a chosen region of the chip and emerging at the upper surface of the chip. The second production phase includes the production of the auxiliary component from a second semiconductor substrate, separate from the first, and then the placement in the cavity of the auxiliary component supported by the second substrate and the mutual adhesion of the second substrate to the upper surface of the chip lying outside the cavity. The second substrate then also forms the protective cover.Type: GrantFiled: December 3, 2002Date of Patent: January 25, 2005Assignee: STMicroelectronics S.A.Inventors: Alexis Farcy, Philippe Coronel, Pascal Ancey, Joaquin Torres
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Patent number: 6617665Abstract: An inductance formed in an integrated circuit chip, formed of a plurality of parallel conductive lines, of optimized width, each conductive line being formed in the thickness of at least one insulating layer, these lines being interconnected by at least one perpendicular conductive segment.Type: GrantFiled: April 18, 2002Date of Patent: September 9, 2003Assignee: STMicroelectronics S.A.Inventors: Alexis Farcy, Vincent Arnal, Joaquim Torres