Abstract: A method for determining that failures in semiconductor test are due to a defect potentially causing a hold time violation in a scan cell in a scan chain, counting the number of potential defects, and, if possible, localizing, and ameliorating hold time defects in a scan chain.

Abstract: In a method for determining a number of possible hold time faults in a scan chain of a DUT, an environmental variable of the scan chain is set to a value believed to cause a hold time fault in the scan chain, and then a pattern is shifted through the scan chain. The pattern has a background pattern of at least n contiguous bits of a first logic state, followed by at least one bit of a second logic state, where n is a length of the scan chain. The number of possible hold time faults in the scan chain can be determined as a difference between i) a clock cycle when the at least one bit is expected to cause a transition at an output of the scan chain, and ii) a clock cycle when the at least one bit actually causes a transition at the output of the scan chain. If a value of the environmental variable at which the scan chain operates correctly can be determined, the location of one or more hold time faults can also be determined.

Abstract: A process for improving design-limited yield by collecting test fail data, converting to electrical faults, and localizing to physical area on semiconductor die. The steps of identifying an area on a wafer containing a fault to enable the analysis of specific defects, accumulating data suitable for yield monitoring analysis based on pattern test failures logged on scan cells in scan chains on automatic test equipment, and translating scan cell and scan chain failure reports to geometric locations of electrical structures on wafers.

Abstract: A method and system is provided for Network-on-Chip (NoC) and other integrated circuit architectures. A configurable fabric circuit (CFC) is interfaced with one or more core circuits and the CFC is responsive to an input signal and capable of reconfiguring the logic circuit in the CFC in accordance with an operational mode determined based on the received input signal to facilitate a core circuit interfaced therewith to carry out an operation consistent with the operational mode.

Abstract: A configurable test access mechanism has a sliced input wrapper, output wrapper and scan configuration wrapper coupled to a circuit under test. The input wrapper efficiently adds a PRPG (pseudo-random pattern generator) function to a scan test structure without impacting speed and power requirements. The output wrapper efficiently adds a MISR (multiple input signature register) functionality for additional test purposes to implement a built-in self-test (BIST) apparatus. Use of existing scan structures to implement the PRPG and MISR functions provides significant savings of circuitry. Variability of test polynomials is easily user programmed.

Abstract: A programmable clock generator (220), which is part of an integrated circuit (IC) (210), provides clock signals (230) and (232) to various components of the IC. The clock generator includes a PLL (322) and one or more choppers (326, 328) which provide a desired waveform to the IC for testing purposes. When used in conjunction with a tester (212, 312), the IC can be scan tested at-speed using slower and less expensive testing equipment.

Abstract: A configurable test access mechanism has a sliced input wrapper (120), output wrapper (160) and scan configuration wrapper (220) coupled to a circuit under test (11). The input wrapper (120) efficiently adds a PRPG (pseudo-random pattern generator) function to a scan test structure without impacting speed and power requirements. The output wrapper (160) efficiently adds a MISR (multiple input signature register) functionality for additional test purposes to implement a built-in self-test (BIST) apparatus. Use of existing scan structures to implement the PRPG and MISR functions provides significant savings of circuitry. Variability of test polynomials is easily user programmed.

Abstract: An integrated circuit contains customer specified logic (12), an embedded core (14), and a plurality of speed path test cells (16 and 18). Once the core (14) is embedded within an integrated circuit (10), not all of the input and output terminals of the embedded core are available at external terminals of the integrated circuit (10). Therefore, the wrapper speed path test cells (16 and 18) are provided. The cell (16) contains two flip-flops (20 and 22) which can be used to launch logic transitions into the embedded core (14) to perform two clock speed path testing. The cell (18) contains flip-flops (26 and 28) which can perform a speed path launch operations to a customer specified logic (12). The cell (16) can perform speed path capture operations for the customer specified logic (12) whereas the cell (18) can perform speed path capture operations for the embedded core (14).

Abstract: Circuitry (20) and an associated an method of operation provides system data (30) and scan data (32) to a latch portion (42) of a data storage element in a reduced setup time period. For each data storage element, a system data transfer gate (22) provides system data (30) to a master latch portion (42) while a scan data transfer gate (24) provides scan data (32) to the master latch portion (42). The scan data (24) and system data transfer (22) gates minimize the set-up time required for data entering the data storage element. Scan chains incorporating the data storage elements include scan data input ports and scan data output ports as well as connections between data storage elements in an associated scan chain. A controller (26) operated by a scan enable signal (38) and a system clock (40) provide control signals to the system data transfer gate (22) and the scan data transfer gate (24) to cause the gates to selectively pass data.

Abstract: The present invention relates to a method (150) of construction of a scannable integrated circuit. The method includes forming a plurality of flip-flops on an integrated circuit where each flip-flop includes a system data transfer gate and a scan data transfer gate, the gates receiving control signals from a controller (152). A clock signal is routed to the flip-flops (154). Preferably, the flip-flops are placed in a manner to optimize the operation of the integrated circuit when in a system mode. The flip-flops are then coupled into scan chains such that the integrated circuit may operate at a scan mode frequency that is equal to or greater than a system mode frequency (156, 158, 160). An alternative method includes forming a plurality of input lines, a plurality of output lines, and a plurality of scan data paths such that each input line starts a balanced scan chain.

Abstract: A data processor (10) has a single test controller (11). The test controller (11) has a test pattern generator portion (26) and a memory verification element (27). The test pattern generator (26) generates and communicates a plurality of test patterns to the plurality of memories (12, 13, and 14) through a second storage device (17). A first storage device (16) is used to store data read from the plurality of memories (12, 13, and 14). The data from the first storage device is selectively accessed by the memory verification element (27) via the bus (31). A bit (32) or more than one bit is used to communicate to external to the processor (10) whether the memories (12, 13, and 14) are operating in an error free manner.

Abstract: A scan chain architecture which has a controller (10), and a multiplexer (24) is used to route test data through functional units (12, 14, 16, 18, 20, and 22). The controller (10) receives as input a serial data stream from an STDI terminal and demultiplexes this data stream to one of the functional units (six functional units are illustrated in FIG. 1). Each of the functional units is considered as one scan chain and therefore FIG. 1 has six scan chains (one for each functional unit). In addition, a seventh scan chain couples all output flip-flops in each of the functional units together between an output of the MUX (24) and the STDO terminal/pin. Therefore, a serial scan of a data stream can be done through one functional unit, the multiplexer (24) and into the output flip-flops of each function unit to make testing easier to set-up. In addition, various new scan chain cells and low power methods are used herein.

Abstract: A low power mode of an integrated circuit (IC) 10 is tested via a test controller 50. The IC 10 is placed in a low power mode where a plurality of pins represented by the pins 82, 72, and 62 are isolated from the internal circuitry, such as CPU 30, via circuits 60, 70, and 80. It is difficult, if not impossible, to test the IC 10 when in a low power mode since all pins are isolated from external circuitry and all clocks are stopped. Therefore, in order to test the low power mode, the test controller 50 can be selectively taken-out of low power mode via a RESET IN signal while all other circuitry in the IC 10 remains in the isolated low power mode. Test controller 50 can then conduct logical low power internal testing of the IC 10 while it is in low power mode and isolated. This testing in done by communicating data via the DATA IN and DATA OUT pins in a serial scan chain manner.

Abstract: A processor (10) has an internal clock circuit (12), a CPU (14), and a test controller (16). The CPU (14) has a low-power mode of operation and a normal mode of operation. When in low power mode, the internal clock circuit isolates the CPU clock (18) from the internal clock (28) and pulls the internal clock (28) to a stable logic state to ensure that the CPU is not changing state and consuming power. The test controller (16) can be in a low power mode along with the CPU (14) or in a normal mode while the CPU (14) is in the low power mode via the test control signal (26). When the CPU is in low power mode and the controller (16) is in normal mode, the controller (16) tests the operation of the circuit (12) to logically ensure that handling of the clock (18) is proper when entering, maintaining and exiting the low power mode of operation.

Abstract: A data processing system (10) has a test controller (12). The test controller (12) has a pattern generator (18) for receiving a seed value and generating many pseudo-random values from the seed value. A re-seed and compare circuit (22) monitors the pattern generator (12) and determined when the seed value repeats in the pseudo-random number sequence generated by the generator (18). Once circuit (22) determines that the seed value has repeated the control circuit (20) allows the generator (18) to clock once more and latches a new seed value into the circuit (22). Therefore, the pattern generator through the compare/store function of circuit (22) and the control of circuit (20) is self re-seeding and generates a longer string of pseudo-random numbers with minimal logic.