Abstract: The method includes forming a first opening in a dielectric layer exposing a source drain region of an SRAM device and forming a second opening in the dielectric layer exposing a source drain region of a logic device, forming a third opening in the dielectric layer exposing a gate of the SRAM device and forming a fourth opening in the dielectric layer exposing a gate of the logic device, forming a first sidewall spacer in the third opening and forming a second sidewall spacer in the fourth opening, recessing a portion of the first sidewall spacer without recessing the second sidewall spacer, forming a strapped contact in the first and third openings, the strapped contact creates an electrical connection between the source drain region of the SRAM device and the gate of the SRAM device, the electrical connection is directly above a remaining portion of the first sidewall spacer.

Abstract: A method of forming a semiconductor structure includes forming a dummy gate above a semiconductor substrate. The dummy gate defines a source-drain region adjacent to the dummy gate and a channel region below the dummy gate. A silicon-germanium layer is epitaxially grown above the source-drain region with a target concentration of germanium atoms. The semiconductor structure is annealed to diffuse the germanium atoms from the silicon-germanium layer into the channel region to form a silicon-germanium channel region.

Abstract: A semiconductor is provided that includes an nFET gate structure straddling over a first nanowire stack and a portion of a first SiGe layer having a first Ge content. The first nanowire stack comprises alternating layers of a tensily strained silicon layer, and a second SiGe layer having a second Ge content that is greater than the first Ge content and being compressively strained. Portions of the tensily strained silicon layers extend beyond sidewalls surfaces of the nFET gate structure and are suspended. The structure further includes a pFET gate structure straddling over a second nanowire stack and another portion of the first SiGe layer. The second nanowire stack comprises alternating layers of the tensily strained silicon layer, and the second SiGe layer. Portions of the second SiGe layers extend beyond sidewalls surfaces of the pFET gate structure and are suspended.

Abstract: Embodiments related to emissive devices for displays are discussed. Some embodiments include light emitting diodes including an electron transport layer core having a tube shape with an inner and an outer sidewall, an emission layer on the inner and outer sidewalls, and a hole transport layer on the emission layer, displays and systems including such light emitting diodes, and methods for fabricating them. Other embodiments include emissive laser devices having an emission layer between a hole transport layer and an electron transport layer and first and second metasurface mirrors adjacent to the hole transport layer and the electron transport layer, respectively, displays and systems including such emissive laser devices, and methods for fabricating them.

Abstract: An epitaxy method includes providing an exposed crystalline region of a substrate material. Silicon is epitaxially deposited on the substrate material in a low temperature process wherein a deposition temperature is less than 500 degrees Celsius. A source gas is diluted with a dilution gas with a gas ratio of dilution gas to source gas of less than 1000.

Abstract: A method of introducing strain in a channel region of a FinFET device includes forming a fin structure on a substrate, the fin structure having a lower portion comprising a sacrificial layer and an upper portion comprising a strained semiconductor layer; and removing a portion of the sacrificial layer corresponding to a channel region of the FinFET device so as to release the upper portion of the fin structure from the substrate in the channel region.

Abstract: The present invention relates generally to a semiconductor device, and more particularly, to a structure and method of forming a compressive strained layer and a tensile strained layer on the same wafer. A lower epitaxial layer may be formed adjacent to a tensile strained layer. An upper epitaxial layer may be formed over a portion of the lower epitaxial layer. Thermal oxidation may convert the upper epitaxial layer to an upper oxide layer, and thermal condensation may causes a portion of the lower epitaxial layer to become a compressive strained layer. The upper oxide layer and a remaining portion of the lower epitaxial layer may be removed, leaving the tensile strained layer and the compressive strained layer.

Abstract: A photovoltaic device including a single junction solar cell provided by an absorption layer of a type IV semiconductor material having a first conductivity, and an emitter layer of a type III-V semiconductor material having a second conductivity, wherein the type III-V semiconductor material has a thickness that is no greater than 50 nm.

Abstract: A semiconductor structure includes a substrate, and a replacement metal gate (RMG) structure is attached to the substrate. The RMG structure includes a lower portion and an upper tapered portion. A source junction is disposed on the substrate and attached to a first low-k spacer portion. A drain junction is disposed on the substrate and attached to a second low-k spacer portion. A first oxide layer is disposed on the source junction, and attached to the first low-k spacer portion. A second oxide layer is disposed on the drain junction, and attached to the second low-k spacer portion. A cap layer is disposed on a top surface layer of the RMG structure and attached to the first oxide layer and the second oxide layer.

Abstract: Non-planar semiconductor devices including semiconductor fins or stacked semiconductor nanowires that are electrostatically enhanced are provided. The electrostatic enhancement is achieved in the present application by epitaxially growing a semiconductor material protruding portion on exposed sidewalls of alternating semiconductor material portions of at least one hard mask capped semiconductor-containing fin structure that is formed on a substrate.

Abstract: Semiconductor devices and methods for making the same includes conformally forming a first spacer on a plurality of fins. A second spacer is conformally formed on the first spacer, the second spacer being formed from a different material from the first spacer. The plurality of fins are etched below a bottom level of the first spacer to form a fin cavity. Material from the first spacer is removed to expand the fin cavity. Fin material is grown directly on the etched plurality of fins to fill the fin cavity.

Abstract: A structure including a plurality of fins etched from a semiconductor substrate, a gate electrode above and perpendicular to the plurality of fins, a pair of sidewall spacers disposed on opposing sides of the gate electrode, a gap fill material above the semiconductor substrate and between the plurality of fins, the gap fill material is directly below the gate electrode and directly below the pair of sidewall spacers, wherein the gate electrode separates the gap fill material from each of the plurality of fins, and an epitaxially grown region above a portion of the plurality of fins not covered by the gate electrode, the EPI region separates the gap fill material from each of the plurality of fins.

Abstract: Electrical fuse (eFuse) and resistor structures and methods of manufacture are provided. The method includes forming metal gates having a capping material on a top surface thereof. The method further includes protecting the metal gates and the capping material during an etching process which forms a recess in a dielectric material. The method further includes forming an insulator material and metal material within the recess. The method further includes forming a contact in direct electrical contact with the metal material.

Abstract: An epitaxy method includes providing an exposed crystalline region of a substrate material. Silicon is epitaxially deposited on the substrate material in a low temperature process wherein a deposition temperature is less than 500 degrees Celsius. A source gas is diluted with a dilution gas with a gas ratio of dilution gas to source gas of less than 1000.

Abstract: A semiconductor structure is provided that contains silicon fins having different heights, while maintaining a reasonable fin height to width ratio for process feasibility. The semiconductor structure includes a first silicon fin of a first height and located on a pedestal portion of a first oxide structure. The structure further includes a second silicon fin of a second height and located on a pedestal portion of a second oxide structure. The first oxide structure and the second oxide structure are interconnected and the second oxide structure has a bottommost surface that is located beneath a bottommost surface of the first oxide structure. Further, the second height of the second silicon fin is greater than the first height of the first silicon fin, yet a topmost surface of the first silicon fin is coplanar with a topmost surface of the second silicon fin.

Abstract: A disposable gate structure is formed over the alternating stack of first semiconductor material portions and second semiconductor material portions. The second semiconductor material portions are removed selective to the first semiconductor material portions to form suspended semiconductor nanowires. Isolated gate structures are formed in regions underlying the disposable gate structure by deposition and recessing of a first gate dielectric layer and a first gate conductor layer. After formation of a gate spacer, source regions, and drain regions, raised source and drain regions are formed on the source regions and the drain regions by selective deposition of a semiconductor material. The disposable gate structure is replaced with a replacement gate structure by deposition and patterning of a second gate dielectric layer and a second gate conductor layer. Distortion of the suspended semiconductor nanowires is prevented by the disposable gate structure and the isolated gate structures.

Abstract: A semiconductor structure that has adjacent transistors that share a common source/drain semiconductor structure. At least one of the adjacent transistors comprising: a vertical channel and a source/drain semiconductor structure connected to the vertical channel such that the source/drain semiconductor structure has a vertical side that is substantially planar with a vertical side of the first vertical channel. The source/drain semiconductor structure extends horizontally from its vertical side farther than the first vertical channel extends from its vertical side such that a width of the source/drain is greater than a width of the first vertical channel. The first source/drain semiconductor structure is located on a layer of substrate and the vertical channel is perpendicular relative to the layer of substrate.

Abstract: A gate structure straddling a plurality of semiconductor material portions is formed. Source regions and drain regions are formed in the plurality of semiconductor material portions, and a gate spacer laterally surrounding the gate structure is formed. Epitaxial active regions are formed from the source and drain regions by a selective epitaxy process. The assembly of the gate structure and the gate spacer is cut into multiple portions employing a cut mask and an etch to form multiple gate assemblies. Each gate assembly includes a gate structure portion and two disjoined gate spacer portions laterally spaced by the gate structure portion. Portions of the epitaxial active regions can be removed from around sidewalls of the gate spacers to prevent electrical shorts among the epitaxial active regions. A dielectric spacer or a dielectric liner may be employed to limit areas in which metal semiconductor alloys are formed.

Abstract: A method of forming a semiconductor device that includes forming an in-situ doped semiconductor material on a semiconductor substrate, and forming fin structures from the in-situ doped semiconductor material. A sacrificial channel portion of the fin structures may be removed, wherein a source region and a drain region portion of the fin structures of the in-situ doped semiconductor material remain. The sacrificial channel portion of the fin structure may then be replaced with a functional channel region.

Abstract: A method of forming a semiconductor structure that includes a tensily strained silicon fin extending upwards from a first portion of a substrate and in an nFET device region, and a SiGe fin structure extending upwards from a second portion of the substrate and in a pFET device region. In accordance with the present application, the SiGe fin structure comprises, from bottom to top, a lower SiGe fin that is relaxed and an upper SiGe fin, wherein the upper SiGe fin is compressively strained and has a germanium content that is greater than a germanium content of the lower SiGe fin.