Abstract: Embodiments herein generally relate to methods, systems and devices for automated assembly of building structures. In at least one embodiment, there is provided a method for automated assembly of building structures, the method comprises analyzing assembly data associated with a building structure; based on the analyzing, determining an assembly sequence for assembling building parts to construct the building structure, wherein the assembly sequence comprises a plurality of assembly tasks; generating robot-specific control instructions, for each of one or more assembly robots in a robotic assembly cell, to execute the assembly sequence; and transmitting the robot-specific control instructions to the one or more assembly robots in the robotic assembly cell.

Abstract: A distributed active, power combining amplifier including at least one main amplifier having a first main portion and a second main portion, at least one peaking amplifier having a first peaking portion and a second peaking portion, and a transformer having a primary side and a secondary side, the primary side having at least a first primary segment, a second primary segment, a third primary segment and a fourth primary segment, wherein the first main portion is coupled to the first primary segment and the second primary segment, the first peaking portion is coupled to the first primary segment or the second primary segment, the second main portion is coupled to the third primary segment and the fourth primary segment, and the second peaking portion is coupled to the third primary segment or the fourth primary segment in a symmetric architecture.

Abstract: An LO clock signal generator includes a fundamental mixer for mixing a source clock signal with a divided version of the source clock signal. The LO clock signal generator also includes a harmonic mixer for mixing the source clock signal with a third harmonic of a divided version of the source clock signal.

Abstract: An LO clock signal generator includes a fundamental mixer for mixing a source clock signal with a divided version of the source clock signal. The LO clock signal generator also includes a harmonic mixer for mixing the source clock signal with a third harmonic of a divided version of the source clock signal.

Abstract: Certain aspects of the present disclosure provide methods and apparatus for reducing phase noise in voltage-controlled oscillators (VCOs). One example VCO generally includes a first resonant circuit comprising an inductor and a first variable capacitive element coupled in parallel with the inductor; and a second variable capacitive element coupled to a center tap of the inductor and further coupled to a reference voltage, wherein the center tap of the inductor is further coupled to a voltage source.

Abstract: An integrated circuit is disclosed that implements a phase-locked loop with charge scaling. In an example aspect, the integrated circuit includes a charge pump, a filter, and a charge manager. The charge pump generates a current signal, and the filter includes a filter capacitor. The charge manager is coupled between the charge pump and the filter. The charge manager includes current-sampling capacitance circuitry and a charge manager controller that is coupled to the current-sampling capacitance circuitry. The current-sampling capacitance circuitry receives the current signal from the charge pump and retains charge from the current signal to create stored charge, with the stored charge including a first charge portion and a second charge portion. The charge manager controller causes the current-sampling capacitance circuitry to communicate the first charge portion to the filter capacitor and causes the current-sampling capacitance circuitry to divert the second charge portion away from the filter capacitor.

Abstract: Certain aspects of the present disclosure generally relate to generating a large electrical resistance. One example circuit generally includes a first transistor having a gate, a source connected with a first node of the circuit, and a drain connected with a second node of the circuit. The circuit may also include a voltage-limiting device connected between the gate and the source of the first transistor, wherein the device, if forward biased, is configured to limit a gate-to-source voltage of the first transistor such that the first transistor operates in a sub-threshold region. The circuit may further include a second transistor configured to bias the voltage-limiting device with a current, wherein a drain of the second transistor is connected with the gate of the first transistor, a gate of the second transistor is connected with the first node, and a source of the second transistor is connected with an electric potential.

Abstract: A method of and system for processing a received signal is disclosed. The method includes generating a corrected radio frequency (RF) signal based on an RF feedback signal and an incoming RF signal, the incoming RF signal includes a wanted signal and an interfering signal. The method also includes down-converting the corrected RF signal to a corrected in-phase baseband signal and a corrected quadrature-phase baseband signal; extracting, based on a baseband signal of an aggressor signal, an in-phase baseband signal of the interfering signal from the corrected in-phase baseband signal; extracting, based on the baseband signal of the aggressor, a quadrature-phase baseband signal of the interfering signal from the corrected quadrature-phase baseband signal; up-converting the extracted interfering signals to produce the RF feedback signal; and generating a second corrected RF signal based on the second RF feedback signal and the incoming RF signal.

Abstract: Various aspects of this disclosure describe the calibration of residual sideband energy in a receiver, for example estimating gain mismatch and phase mismatch in in-phase (I) and quadrature-phase channels (Q) of a receiver. An input to the receiver is supplied with an input signal generated to comprise a bandwidth including a plurality of frequencies, such as a linear frequency modulation signal. An output signal of the receiver is filtered by a filter programmed to be matched to the input signal, and estimates of gain error and phase error in I and Q channels of the receiver are determined from the filtered outputs.

Abstract: Certain aspects of the present disclosure provide methods and apparatus for reducing phase noise in voltage-controlled oscillators (VCOs). One example VCO generally includes a first resonant circuit comprising an inductor and a first variable capacitive element coupled in parallel with the inductor; and a second variable capacitive element coupled to a center tap of the inductor and further coupled to a reference voltage, wherein the center tap of the inductor is further coupled to a voltage source.

Abstract: Power conservation in a radio frequency front end of a user equipment (UE) during wireless local area network (WLAN) communication is achieved by adjusting a power mode of the radio frequency front end. In one instance, the UE determines a signal strength of a received frame of a packet during a short training field of a preamble of the received frame. The determining occurs when a WLAN receiver is operating in a low power mode. The UE then switches the WLAN receiver to a high power mode during the short training field of the preamble or during a first segment of a long training field of the preamble when the signal strength is above a predetermined signal strength.

Abstract: Various aspects of this disclosure describe switched-capacitor circuits in a PLL. Examples include routing current from a first current source through a capacitor to ground during a first clock phase, routing current from a second current source through the capacitor to ground during a second clock phase, and transferring charge on the capacitor to a loop filter capacitor during a third clock phase. The first current source may generate current responsive to UP error samples from a phase/frequency detector (PFD), and the second current source generates current responsive to DN error samples from the PFD.

Abstract: A differential switched capacitor device, including: first and second terminals; first and second branches coupled between the first and second terminals, each branch of the first and the second branches comprising at least one capacitor; and first and second switches, each switch of the first and second switches disposed in each branch of the first and second branches.

Abstract: A MOS capacitor with improved linearity is disclosed. In an exemplary embodiment, an apparatus includes a main branch comprising a first signal path having a first capacitor pair connected in series with reversed polarities and a second signal path having a second capacitor pair connected in series with reversed polarities, the first and second signal paths connected in parallel. The apparatus also includes an auxiliary branch comprising at least one signal path having at least one capacitor pair connected in series with reversed polarities and connected in parallel with the main branch. In an exemplary embodiment, the capacitors are MOS capacitors.

Abstract: A two-walled coupled inductor includes an outer wall and an inner wall separated by a slit. The outer wall has a first width and the inner wall has a second width. The inner wall and the outer wall may be configured to be coupled to oscillator circuitry. The two-walled coupled inductor may include an electrically conductive stub coupled to the outer wall to be coupled to a power supply. A common mode current flows through the outer wall, and the stub if one is present, and a differential mode current flows through both the outer wall and the inner wall, but not the stub. The first and second widths, and dimensions of the stub, may be sized to increase an inductance of the common mode compared to an inductance of the differential mode, thereby reducing phase noise of the inductor-based resonator.

Abstract: A two-walled coupled inductor includes an outer wall and an inner wall separated by a slit. The outer wall has a first width and the inner wall has a second width The inner wall and the outer wall may be configured to be coupled to oscillator circuitry. The two-walled coupled inductor may include an electrically conductive stub coupled to the outer wall to be coupled to a power supply. A common mode current flows through the outer wall, and the stub if one is present, and a differential mode current flows through both the outer wall and the inner wall, but not the stub. The first and second widths, and dimensions of the stub, may be sized to increase an inductance of the common mode compared to an inductance of the differential mode, thereby reducing phase noise of the inductor-based resonator.

Abstract: A method and apparatus for minimizing transmit signal interference is provided. The method includes the steps of: receiving a signal and amplifying the received signal. The received signal is then mixed with an intermediate frequency signal to obtain a baseband modulated signal. The baseband modulated signal is first filtered in an RC filter. The resulting signal is then divided by a preselected amount and the first divided portion is sent to a main path of a biquad filter, which produces a first stage biquad filtered signal. The second portion of the divided signal is sent to an auxiliary path of the biquad filter, and produces a second filtered signal. The first and second signals are then recombined and sent to the second stage of the biquad filter, where further filtering takes place.

Abstract: A method and apparatus are disclosed for filtering a signal, such as a transmit communication signal with a configurable notch filter. The configurable notch filter may attenuate a set of frequencies near a selected notch frequency. In some embodiments, the configurable notch filter may include a variable resistor, a variable capacitor, a first inductor, and a second inductor. The variable resistor may be configured to compensate for resistive losses within the configurable notch filter. The variable capacitor may be configured to determine the set of frequencies to be attenuated.

Abstract: Differential crystal oscillator circuits are disclosed that may provide low-power, low phase noise operation, and prevent latching at low frequency by providing a low impedance DC path using active super diodes.

Abstract: Certain aspects of the present disclosure provide techniques and apparatus for generating multiple oscillating signals. One example circuit generally includes a first voltage-controlled oscillator (VCO) having a first inductor and a second VCO having a second inductor in parallel with a third inductor, wherein the second and third inductors are disposed inside a loop of the first inductor and may behave as a magnetic dipole. The loop of the first inductor may be symmetrical, and a combined geometry of loops of the second and third inductors may be symmetrical. The coupling coefficient (k) between the first inductor and a combination of the second and third inductors may be small (e.g., k<0.01), due to the symmetrical geometry of the circuit layout. With a smaller k, the first and second VCOs' inductors may be placed closer to one another, thereby reducing an area consumed by the two VCOs.