Abstract: An apparatus includes a main amplifier configured to receive an input signal. The main amplifier is also configured to generate an output signal. The apparatus also includes an auxiliary path configured to phase-shift the input signal to generate a cancellation signal to reduce or cancel a blocker component of the output signal.

Abstract: A method and an apparatus for canceling EM coupling are provided. The apparatus includes a ring structure at least partially surrounding an EM circuit. A negative transconductance circuit is coupled to ends of the ring structure. The negative transconductance circuit is configured to cancel an EM coupling to the EM circuit at a frequency. The method includes generating a plurality of settings for a negative transconductance circuit and tuning the negative transconductance circuit to one of the plurality of settings for the negative transconductance circuit to cancel an EM coupling to an EM circuit at a frequency.

Abstract: A method and an apparatus for canceling EM coupling are provided. The apparatus includes a ring structure at least partially surrounding an EM circuit. A negative transconductance circuit is coupled to ends of the ring structure. The negative transconductance circuit is configured to cancel an EM coupling to the EM circuit at a frequency. The method includes generating a plurality of settings for a negative transconductance circuit and tuning the negative transconductance circuit to one of the plurality of settings for the negative transconductance circuit to cancel an EM coupling to an EM circuit at a frequency.

Abstract: Systems, apparatus and methods in a mobile device to multiplex two global navigation satellite system (GNSS) signals on a single hardware receiver chain are presented. The GNSS signals may come from a common GNSS system on two bands of two different GNSS systems overlapping on a common band. A duty cycle of the GNSS signals may be based on a harmonic being within one of the first band and the second band. The duty cycle may be based on signal quality, such as indicating a jammed or non jammed signal. The duty cycle may be of unequal proportions and less than 100% such that the receiver chain is idle for a percentage of time.

Abstract: A method and apparatus are disclosed for mitigating a frequency spur included with a transmitter output signal from a wireless device. For at least some embodiments, the wireless device may include an auxiliary synthesizer to generate a spur cancellation signal to be summed with the transmitter output signal to cancel or reduce the frequency spur. The auxiliary synthesizer may also generate an auxiliary clock signal to demodulate a received communication signal. In some embodiments, the transmitter output signal may be looped back to a receiver of the wireless device to determine whether the frequency spur is reduced below a threshold. Data from the receiver may be used to modify the spur cancellation signal.

Abstract: An apparatus includes a main low noise amplifier and an auxiliary low noise amplifier. The auxiliary low noise amplifier is coupled in parallel with the main low noise amplifier. The auxiliary low noise amplifier includes a common source degeneration resistor.

Abstract: An apparatus includes a main amplifier configured to receive an input signal. The main amplifier is also configured to generate an output signal. The apparatus also includes an auxiliary path configured to phase-shift the input signal to generate a cancellation signal to reduce or cancel a blocker component of the output signal.

Abstract: A MOS capacitor with improved linearity is disclosed. In an exemplary embodiment, an apparatus includes a main branch comprising a first signal path having a first capacitor pair connected in series with reversed polarities and a second signal path having a second capacitor pair connected in series with reversed polarities, the first and second signal paths connected in parallel. The apparatus also includes an auxiliary branch comprising at least one signal path having at least one capacitor pair connected in series with reversed polarities and connected in parallel with the main branch. In an exemplary embodiment, the capacitors are MOS capacitors.

Abstract: A divide-by-two divider circuit receives a differential input signal and outputs four rail-to-rail, twenty-five percent duty cycle signals, where the frequency of the output signals is half of the frequency of the input signal. Each latch can output its output signals into loads of at least 15 fF at a frequency of at least 3 GHz so that each output signal has a phase noise of better than 160 dBc/Hz, while the latch consumes less than 0.7 mW over PVT from a supply voltage less than 1.0 volt. Each latch has a cross-coupled pair of P-channel transistors and two output signal generating branches. A static current blocking circuit in each branch prevents current flow in the branch during times when the branch is not switching its output signal. The input node of the latch is capacitively coupled to a signal source, and the DC voltage on the node is set by a bias circuit.

Abstract: A combination equalizer and automatic gain control (AGC) is provided for high-speed receivers. The combination circuit comprises a first AGC having an input to accept a communication signal and an input to accept a first control signal. The first AGC modifies the communication signal gain in response to the first control signal, to supply a first stage signal at an output. An equalizer has an input to accept the first stage signal and an input to accept a second control signal. The equalizer modifies the frequency characteristics of the first stage signal in response to the second control signal, to supply an equalized signal at an output. A second AGC has an input to accept the equalized signal and an input to accept a third control signal. The second AGC modifies the equalized signal gain in response to the third control signal, to supply a second stage signal at an output.