Abstract: A method for branch prediction, the method comprising, receiving a branch wrong guess instruction having a branch wrong guess instruction address and data including an opcode and a branch target address, determining whether the branch wrong guess instruction was predicted by a branch prediction mechanism, sending the branch wrong guess instruction to an execution unit responsive to determining that the branch wrong guess instruction was predicted by the branch prediction mechanism, and receiving and decoding instructions at the branch target address.

Abstract: A method is provided for maintaining system state in semiconductor device having a first chip and a second chip, which are physically conjoined to form a stacked structure, wherein the first chip includes functional circuitry, and the second chip includes control circuitry for capturing and restoring a microarchitecture state of the functional circuitry of the first chip. The method includes initializing a system state of the semiconductor device and entering a wait state for a state capture triggering event. In response to an occurrence of a state capture triggering event, state data representing a current system state of the functional circuitry on the first chip is captured. The captured state data is transferred to the second chip through a system state I/O (input/output) interface of the second chip under control of the control circuitry on the second chip. A copy of the captured state data is then stored in a memory.

Abstract: Three-dimensional (3-D) processor structures are provided which are constructed by connecting processors in a stacked configuration. For example, a processor system includes a first processor chip comprising a first processor, and a second processor chip comprising a second processor. The first and second processor chips are connected in a stacked configuration with the first and second processors connected through vertical connections between the first and second processor chips. The processor system further includes a mode control circuit to selectively configure the first and second processors of the first and second processor chips to operate in one of a plurality of operating modes, wherein the processors can be selectively configured to operate independently, to aggregate resources, to share resources, and/or be combined to form a single processor image.

Abstract: Three-dimensional (3-D) processor devices are provided, which are constructed by connecting processors in a stacked configuration. For instance, a processor system includes a first processor chip comprising a first processor and a second processor chip comprising a second processor. The first and second processor chips are connected in a stacked configuration with the first and second processors connected through vertical connections between the first and second processor chips. The processor system further includes a mode control circuit to selectively operate the processor system in one of a plurality of operating modes. For example, in a one mode of operation, the first and second processors are configured to implement a run-ahead function, wherein the first processor operates a primary thread of execution and the second processor operates a run-ahead thread of execution.

Abstract: Three-dimensional (3-D) processor devices are provided, which are constructed by connecting processors in a stacked configuration. For instance, a processor system includes a first processor chip comprising a first processor and a second processor chip comprising a second processor. The first and second processor chips are connected in a stacked configuration with the first and second processors connected through vertical connections between the first and second processor chips. The processor system further includes a mode control circuit to selectively operate the processor system in one of a plurality of operating modes. For example, in a one mode of operation, the first and second processors are configured to implement a run-ahead function, wherein the first processor operates a primary thread of execution and the second processor operates a run-ahead thread of execution.

Abstract: A method is provided for maintaining system state in semiconductor device having a first chip and a second chip, which are physically conjoined to form a stacked structure, wherein the first chip includes functional circuitry, and the second chip includes control circuitry for capturing and restoring a microarchitecture state of the functional circuitry of the first chip. The method includes initializing a system state of the semiconductor device and entering a wait state for a state capture triggering event. In response to an occurrence of a state capture triggering event, state data representing a current system state of the functional circuitry on the first chip is captured. The captured state data is transferred to the second chip through a system state I/O (input/output) interface of the second chip under control of the control circuitry on the second chip. A copy of the captured state data is then stored in a memory.

Abstract: Three-dimensional processing systems are provided which have multiple layers of conjoined chips, wherein at least one chip layer has calibration control circuitry that is dedicated to calibrating/configuring one or more functional chip layers, and/or performance instrumentation control circuitry for testing and collecting performance data of one or more functional chip layers.

Abstract: Three-dimensional processing systems are provided having one or more layers with circuitry that is dedicated to scanning and testing of other system layers, and which enables dynamic checkpointing, fast context switching and fast recovery of system state. For example, a semiconductor device includes a first chip and a second chip, which are physically conjoined to form a stacked structure. The first chip includes functional circuitry. The functional circuitry includes a plurality of scan cells such as scanable flip-flop and latches. The second chip includes scan testing circuitry, and a scan testing I/O (input/output) interface. The scan cells of the first chip are connected to the scan testing I/O interface of the second chip. The scan testing circuitry on the second chip operates to dynamically configure electrical connections between the scan cells on the first chip to form scan chains or scan rings for testing portions of the functional circuitry on the first chip.

Abstract: Three-dimensional processing systems are provided which have multiple layers of conjoined chips, wherein one or more chip layers include processor cores that share cache hierarchies over multiple chip layers. The caches can be partitioned, conjoined, and managed according to various sets of rules and configurations.

Abstract: Three-dimensional (3-D) processor structures are provided which are constructed by connecting processors in a stacked configuration. For example, a processor system includes a first processor chip comprising a first processor, and a second processor chip comprising a second processor. The first and second processor chips are connected in a stacked configuration with the first and second processors connected through vertical connections between the first and second processor chips. The processor system further includes a mode control circuit to selectively configure the first and second processors of the first and second processor chips to operate in one of a plurality of operating modes, wherein the processors can be selectively configured to operate independently, to aggregate resources, to share resources, and/or be combined to form a single processor image.

Abstract: Multi-dimensional memory architectures are provided having access wiring structures that enable different access patterns in multiple dimensions. Furthermore, three-dimensional multiprocessor systems are provided having multi-dimensional cache memory architectures with access wiring structures that enable different access patterns in multiple dimensions.

Abstract: A computer processor system includes a plurality of multi-chip systems that are physically aggregated and conjoined. Each multi-chip system includes a plurality of chips that are conjoined together, and a local interconnection and input/output wiring layer. A global interconnection network is connected to the local interconnection and input/output wiring layer of each multi-chip system to interconnect the multi-chip systems together. One or more of the multi-chip systems includes a plurality of processor chips that are conjoined together.

Abstract: Multi-dimensional memory architectures are provided having access wiring structures that enable different access patterns in multiple dimensions. Furthermore, three-dimensional multiprocessor systems are provided having multi-dimensional cache memory architectures with access wiring structures that enable different access patterns in multiple dimensions.

Abstract: Three-dimensional processing systems are provided which have multiple layers of conjoined chips, wherein at least one chip layer has calibration control circuitry that is dedicated to calibrating/configuring one or more functional chip layers, and/or performance instrumentation control circuitry for testing and collecting performance data of one or more functional chip layers.

Abstract: Three-dimensional processing systems are provided which have multiple layers of conjoined chips, wherein one or more chip layers include processor cores that share cache hierarchies over multiple chip layers. The caches can be partitioned, conjoined, and managed according to various sets of rules and configurations.

Abstract: Three-dimensional processing systems are provided having one or more layers with circuitry that is dedicated to scanning and testing of other system layers, and which enables dynamic checkpointing, fast context switching and fast recovery of system state. For example, a semiconductor device includes a first chip and a second chip, which are physically conjoined to form a stacked structure. The first chip includes functional circuitry. The functional circuitry includes a plurality of scan cells such as scanable flip-flop and latches. The second chip includes scan testing circuitry, and a scan testing I/O (input/output) interface. The scan cells of the first chip are connected to the scan testing I/O interface of the second chip. The scan testing circuitry on the second chip operates to dynamically configure electrical connections between the scan cells on the first chip to form scan chains or scan rings for testing portions of the functional circuitry on the first chip.

Abstract: A three-dimensional (3-D) processor system includes a first processor chip and a second processor chip in a stacked configuration. The first processor chip includes a first processor having a first set of state registers. The second processor chip includes a second processor having a second set of state registers that corresponds to the first set of state registers. The first and second processors are connected through vertical connections between the first and second processor chips. A mode control circuit operates the processor system in one of a plurality of operating modes. In one mode of operation, the first processor is active and the second processor is inactive, and the first processor operates at a speed greater than a maximum safe speed of the first processor, and the first processor uses the second set of state registers of the second processor to checkpoint a state of the first processor.

Abstract: A three-dimensional (3-D) processor system includes a first processor chip and a second processor chip in a stacked configuration. The first processor chip includes a first processor having a first set of state registers. The second processor chip includes a second processor having a second set of state registers that corresponds to the first set of state registers. The first and second processors are connected through vertical connections between the first and second processor chips. A mode control circuit operates the processor system in one of a plurality of operating modes. In one mode of operation, the first processor is active and the second processor is inactive, and the first processor operates at a speed greater than a maximum safe speed of the first processor, and the first processor uses the second set of state registers of the second processor to checkpoint a state of the first processor.

Abstract: Multi-dimensional memory architectures are provided having access wiring structures that enable different access patterns in multiple dimensions. Furthermore, three-dimensional multiprocessor systems are provided having multi-dimensional cache memory architectures with access wiring structures that enable different access patterns in multiple dimensions.

Abstract: Multi-dimensional memory architectures are provided having access wiring structures that enable different access patterns in multiple dimensions. Furthermore, three-dimensional multiprocessor systems are provided having multi-dimensional cache memory architectures with access wiring structures that enable different access patterns in multiple dimensions.