Abstract: A data storage device may be configured to direct access to at least a portion of a host memory of a host device. For example, the data storage device may store data at the host memory, such as data predicted to be subject to a read request from the host device. When the data storage device receives a read request from the host device to read the data, the data storage device may send an indication to the host device to enable the host device to read the data directly from the host memory.

Abstract: A memory array includes strings that are configured to store keywords and inverse keywords corresponding to keys according to content addressable memory (CAM) storages schemes. A read circuit performs a CAM read operation over a plurality of iterations to determine which of the keywords are matching keywords that match a target keyword. During the iterations, a read controller biases word lines according to a plurality of modified word line bias setting that are each modified from an initial word line bias setting corresponding to the target keyword. At the end of the CAM read operation, the read controller detects which of the keywords are matching keywords, even if the strings are storing the keywords or inverse keywords with up a certain number of bit errors.

Abstract: An apparatus and method of providing direct access to a non-volatile memory of a non-volatile memory device and detecting potential security violations are provided. A method for providing access to a non-volatile memory of a non-volatile memory device may include tracking a parameter related to a plurality of direct access transactions of the non-volatile memory. A threshold behavior pattern of the host activity may be determined based upon the tracked parameters. The direct access transactions may be reviewed to determine whether the threshold behavior pattern is exceeded.

Abstract: A Data Storage Device (DSD) includes a Non-Volatile Memory (NVM) for storing data. A processor of the DSD receives a command from a host to access data in the NVM, and performs the command to access data in the NVM. The DSD further includes a host-trusted module functionally isolated from at least a portion of the DSD. The host-trusted module is configured to receive an instruction from the host, and perform an operation based on the instruction. According to one aspect, the operation includes a predetermined atomic operation to modify data stored in the NVM.

Abstract: A method of transitioning between a sleep mode for a storage device to reduce power consumption and to increase responsiveness includes collecting one or more recent parameters related to host-storage device workload. The host-storage device workload is correlated to project a next host idle time. A transition between a storage sleep mode is determined.

Abstract: A system and method for reducing performance penalties of a host that is supplying a host memory buffer (HMB) for use by a storage device. The method may include modeling desired HMB access timing by the storage device in an initial offline analysis for multiple classes of workloads, periodically updating the access timing data stored in the storage device based on actual use and using the current HMB access timing information to modify storage device access to the HMB on the host. The system may include a storage device controller that quantifies different HMB access timing for different host workloads based on individual HMB regions.

Abstract: The disclosure relates in some aspects to on-chip processing circuitry formed within the die of a non-volatile (NVM) array to perform data searches. In some aspects, the die includes components configured to sense wordlines of stored data in the NVM array by applying voltages on the wordlines serially, and then search for an input data pattern within the serially-sensed wordlines. In some examples, the components of the die include latches and circuits configured to perform bitwise latch logic search operations. In other examples, the search components are configured with under-the-array or next-to-the-array dedicated search circuitry that uses registers and/or random access memory (RAM). Other aspects relate to a separate controller device for controlling the on-chip NVM search operations. For example, the controller may determine whether to search for data using search components of the NVM die or processors of the controller based, e.g., on a degree of fragmentation of data.

Abstract: A storage device may utilize de-centralized latch management to remove functions from the device controller to the memory die. NAND die located on a common bus may share a pool of latches with one die acting as a proxy or manager for the other die. A bridge or bridges may be used between NAND connections to allow additional die to be controlled by a leader die for the partially de-centralized management of latches. The latch management operations may include a sequence of commands/operations performed by the leader die.

Abstract: Technology is described herein for operating non-volatile storage. One aspect is an apparatus that dynamically changes an allocation of host memory that is for the exclusive use of a non-volatile memory controller. The non-volatile memory controller may make a runtime request for additional host memory that is for the exclusive use of the non-volatile memory controller. The non-volatile memory controller might use the additional host memory for a task such as garbage collection, and then release the host memory back to the host.

Abstract: Aspects of the disclosure provide for managing data storage at a solid state device (SSD) based on an expected storage term (EST) of the data. Methods and apparatus receive, from a host, data to be stored in a non-volatile memory (NVM) of the SSD, determine the EST of the data, select a location in the NVM to store the data based on the EST, and write the data in the selected location. The methods and apparatus may further determine whether the EST has expired, mark the data if the EST has expired, determine whether a time to release (TTR) has arrived after the EST has expired, and delete the marked data after the TTR has arrived or store the data in a different location in the NVM for a term longer than the EST if the TTR has not arrived.

Abstract: The disclosure relates in some aspects to a controller of a data storage device, such as the controller of a solid state device (SSD) having non-volatile memory (NVM). In some aspects, the controller operates to prevent or reduce page faults in the host device. In one example, an outer mapping table of a set of page tables of a host device stores pointers to an inner mapping table in the SSD controller. The pointers are provided within memory access requests sent from the host to the SSD. The inner table maps the pointers to physical addresses in the SSD. The SSD detects page faults by identifying pointers that do not have corresponding entries in the inner table. The SSD allocates physical addresses to accommodate such access requests, then executes the requests on behalf of the host device. In this manner, the page fault is transparent to the host.

Abstract: Memory systems that can predict a physical address associated with a logical address, and methods for use therewith, are described herein. In one aspect, the memory system predicts a physical address for a logical address that follows a sequence of random logical addresses. The predicted physical address could be a physical location where the data for the logical address is predicted to be stored. In some cases, the host data can be returned without accessing a management table. The predicted physical address is not required to be the location of the data to be returned to the host for the logical address. In one aspect, the memory system predicts a physical address at which information is stored that may be used to ultimately provide the data for the logical address, such as a location in the management table.

Abstract: A method and system for user experience event processing and analysis are provided. In one embodiment, a computing device correlates detected pre-defined user experience events with data indicating activity of a storage device over a time period and generates an analysis of the correlation. In another embodiment, a computing device compares first and second recorded videos to identify differences, wherein the first and second recorded videos are synchronized based on content rather than time, correlates the differences with the data indicating activity of a storage device of a host device, and generates an analysis of the correlation. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.

Abstract: Embodiments of the present disclosure generally relate to a storage device and method of managing flash memory read operations of a storage device. In one embodiment, a method of retrieving information stored in a storage device comprises determining a timing of a next host read command for a flash memory die. If there is a storage device initiated read request for the flash memory die is determined. In response to an identification of the storage device initiated read request, a random cache read operation is initiated with the storage device initiated read request bound with the next host read command.

Abstract: Technology is described herein for operating non-volatile storage. One aspect is an apparatus that dynamically changes an allocation of host memory that is for the exclusive use of a non-volatile memory controller. The non-volatile memory controller may make a runtime request for additional host memory that is for the exclusive use of the non-volatile memory controller. The non-volatile memory controller might use the additional host memory for a task such as garbage collection, and then release the host memory back to the host.

Abstract: Technology is disclosed for reading non-volatile memory when a host does not need perfect data. By allowing the memory to return data with some errors, the data will be provided to the host much quicker. Therefore, in response to one or more host read commands, the memory system returns multiple copies of the data over time, progressively getting better so that later in time copies of the data have lower number of errors. The host decides when the error rate is good enough and stops the process (or ignores the rest of the results).

Abstract: In order to write data to a storage system accessible with a first and second file system, a manager receives a data write request associated with a file. The manager determines if a function supported by the second file system is needed to complete the write request. If so, the file is opened and extended with the first file system. The file is then opened and written to by the second file system. The file is truncated by the first file system, and closed by both file systems. If the second file system function is not needed, the file is opened, written, and closed by the first file system. In order to read data from a storage system using a function supported by the second file system, the second file system's cached storage system index is updated, and then the file is opened, read, and closed by the second file system.

Abstract: Memory systems that can predict a physical address associated with a logical address, and methods for use therewith, are described herein. In one aspect, the memory system predicts a physical address for a logical address that follows a sequence of random logical addresses. The predicted physical address could be a physical location where the data for the logical address is predicted to be stored. In some cases, the host data can be returned without accessing a management table. The predicted physical address is not required to be the location of the data to be returned to the host for the logical address. In one aspect, the memory system predicts a physical address at which information is stored that may be used to ultimately provide the data for the logical address, such as a location in the management table.

Abstract: Technology is described herein for operating non-volatile storage. In one aspect, a memory controller replaces an original data buffer pointer(s) to a host memory data buffer(s) with a replacement data buffer pointer(s) to a different data buffer(s) in the host memory. The original data buffer pointer(s) may be associated with a specific read command. For example, the original data buffer pointer(s) may point to data buffer(s) to which data for some range of logical addresses (which may be read from the non-volatile storage) is to be transferred by a memory controller of the non-volatile storage. The replacement data buffer pointer(s) could be associated with a different read command. However, it is not required for the replacement data buffer pointer(s) to be associated with a read command. The replacement data buffer pointer(s) may point to a region of memory that is allocated for exclusive use of the memory controller.

Abstract: Technology is described herein for operating non-volatile storage. In one aspect, a memory controller replaces an original data buffer pointer(s) to a host memory data buffer(s) with a replacement data buffer pointer(s) to a different data buffer(s) in the host memory. The original data buffer pointer(s) may be associated with a specific read command. For example, the original data buffer pointer(s) may point to data buffer(s) to which data for some range of logical addresses (which may be read from the non-volatile storage) is to be transferred by a memory controller of the non-volatile storage. The replacement data buffer pointer(s) could be associated with a different read command. However, it is not required for the replacement data buffer pointer(s) to be associated with a read command. The replacement data buffer pointer(s) may point to a region of memory that is allocated for exclusive use of the memory controller.