Abstract: Systems and methods are disclosed for identifying and compressing rarely used data. A storage module may include a memory and a storage controller in operative communication with the memory. The storage controller is configured to identify an access of data stored at a first portion of the memory; determine, based on a first value of the access counter associated with the identified access and a second value of the access counter, that an age of the data stored at the first portion of the memory exceeds a threshold; identify data stored at a second portion of the memory that is associated with a third value of the access counter, where the third value of the access counter is within a range of the first value of the access counter; and compress together at least the data stored at the first and second portions of the memory.

Abstract: In a flash memory two or more pages in a plane are read in rapid succession by maintaining global word line voltages throughout multiple page reads, and by simultaneously transitioning the old selected word line from a discrimination voltage to a read voltage and transitioning the new selected word line from the read voltage to a discrimination voltage.

Abstract: A method includes, in response to a first write command corresponding to first data and a first context which is identifiable with a first identifier and to a second write command corresponding to second data and a second context identifiable with a second identifier, determining whether the first identifier of the first context matches the second identifier of the second context. The method also includes, if the first identifier of the first context is determined to match the second identifier of the second context, forming a compression group of data including the first data and the second data, and generating compressed data corresponding to the compression group of data.

Abstract: A method includes determining a first logical block address (LBA) range of a first set of data units of a first candidate block of the memory. The method also includes determining a second LBA range of a second set of data units of a relocation block of the memory. The method also includes determining that the first LBA range matches the second LBA range. The method further includes relocating first valid data of the first candidate block to the relocation block of the memory in response to determining that the first LBA range matches the second LBA range, where the first LBA range corresponds to multiple LBAs.

Abstract: In a flash memory two or more pages in a plane are read in rapid succession by maintaining global word line voltages throughout multiple page reads, and by simultaneously transitioning the old selected word line from a discrimination voltage to a read voltage and transitioning the new selected word line from the read voltage to a discrimination voltage.

Abstract: A storage module and method for managing logical-to-physical address mapping are disclosed. In one embodiment, a storage module is provided comprising a memory having a plurality of wordlines and a controller. The controller is configured to use a logical-to-physical address map to convert a logical address to a physical address of a wordline. A plurality of logical addresses in the map point to a single wordline, and the single wordline contains both data associated with the plurality of logical addresses and information about where to find each of the plurality of logical addresses in the single wordline . Storing the information about where to find each of the plurality of logical addresses in the wordline itself avoids the delay and complexity of using a larger logical-to-physical address map or multiple maps.

Abstract: Techniques are presented to allow non-volatile memory system to operate more efficiently by determining ranges of logical addresses that a host typically accesses as together. For example, the system's controller can determine that the host always, or most always, writes or reads a contiguous set of logical addresses as a single unit. The controller can exploit this information by operating on these ranges as single a unit for data operations it performs. To take one example, the memory system can treat such ranges as single units for on-system data compression prior to writing the data to non-volatile memory, thereby increasing the efficiency of such data compression.

Abstract: A temperature-controlled storage module is disclosed. In one embodiment, a storage module is provided comprising a memory, a temperature sensor, a thermoelectric cooler, and a controller. The controller compares a temperature reading from the temperature sensor to a target temperature. If the temperature reading differs from the target temperature, the controller activates the thermoelectric cooler. For example, if the temperature reading is higher than the target temperature, the thermoelectric cooler can be activated to cool the memory. This allows the memory (e.g., NAND die(s)) to operate in a narrow range of temperatures providing better system tradeoffs on memory (e.g., NAND) characteristics.

Abstract: A temperature-controlled storage module is disclosed that cools memory prior to a data burst. In one embodiment, a storage module is provided comprising a memory, a temperature sensor, a thermoelectric cooler, and a controller. The controller determines that a host in communication with the storage module is about to send a burst of data and then activates the thermoelectric cooler to cool the memory. The controller can determine that the host is about to send a burst of data either from a notification from the host or by making an inference based on write activity from the host over a period of time. This enables higher parallelism during the burst, hence improving the burst's performance.

Abstract: A method is performed in a data storage device that includes a controller coupled to a non-volatile memory. The non-volatile memory includes a group of storage elements. Each storage element is configured to store multiple data bits. Data is sent from the controller to the non-volatile memory and first bits corresponding to a first portion of the data are stored into the group of storage elements during a first write stage. Each storage element of the group of storage elements stores at least one bit of the first bits upon completion of the first write stage. Second bits corresponding to a second portion of the data are sent to a second memory without sending the first bits to the second memory. The second bits are retrieved from the second memory and at least the second bits are stored into the group of storage elements during a second write stage.

Abstract: In a flash memory two or more pages in a plane are read in rapid succession by maintaining global word line voltages throughout multiple page reads, and by simultaneously transitioning the old selected word line from a discrimination voltage to a read voltage and transitioning the new selected word line from the read voltage to a discrimination voltage.

Abstract: A computing device and method for predicting low memory conditions are disclosed. In one embodiment, a computing device is provided having volatile memory, non-volatile memory, and a processor. The processor generates a metric predictive of an upcoming low-memory condition in the volatile memory. The processor then compares the metric to a threshold. If the metric exceeds the threshold, the processor creates free space in the volatile memory. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.

Abstract: Systems and methods of memory management storage to a host device are disclosed. A method is performed in a data storage device with a non-volatile memory and a controller operative to manage the non-volatile memory and to generate management data for managing the non-volatile memory. The method includes performing, at a given time, originating at the controller data management transfer to a host device or originating at the controller data management retrieval from the host device.

Abstract: A method of servicing a command sent from a host device file system (HDFS) within a host device (HD) by a local storage device (LSD) in communication with the HD is described. The method includes receiving a first command at the LSD instructing the LSD to execute an operation on associated logical addresses. If the first command is associated with at least a first set of logical addresses, the method includes servicing the first command by the LSD at least by way of sending a second command to a device (RD) external to the LSD that instructs the RD to execute an operation on memory locations within the RD. If the first command is not associated with the first set of logical addresses, the method includes servicing the first command by the LSD only by way of operations executed by the LSD on memory locations within the LSD.

Abstract: A method is performed in a data storage device that includes a controller coupled to a non-volatile memory. The non-volatile memory includes a group of storage elements. Each storage element is configured to store multiple data bits. Data is sent from the controller to the non-volatile memory and first bits corresponding to a first portion of the data are stored into the group of storage elements during a first write stage. Each storage element of the group of storage elements stores at least one bit of the first bits upon completion of the first write stage. Second bits corresponding to a second portion of the data are sent to a second memory without sending the first bits to the second memory. The second bits are retrieved from the second memory and at least the second bits are stored into the group of storage elements during a second write stage.

Abstract: A method is performed in a data storage device that includes a controller coupled to a non-volatile memory. The non-volatile memory includes a group of storage elements. Each storage element is configured to store multiple data bits. Data is sent from the controller to the non-volatile memory and first bits corresponding to a first portion of the data are stored into the group of storage elements during a first write stage. Each storage element of the group of storage elements stores at least one bit of the first bits upon completion of the first write stage. Second bits corresponding to a second portion of the data are sent to a second memory without sending the first bits to the second memory. The second bits are retrieved from the second memory and at least the second bits are stored into the group of storage elements during a second write stage.

Abstract: A data storage device includes a controller coupled to a non-volatile memory having a three-dimensional (3D) configuration. The non-volatile memory includes a group of storage elements. Each storage element is configured to store multiple data bits. Data is sent from the controller to the non-volatile memory and first bits corresponding to a first portion of the data are stored into the group of storage elements during a first write stage. Each storage element of the group of storage elements stores at least one bit of the first bits upon completion of the first write stage. Second bits corresponding to a second portion of the data are sent to a second memory without sending the first bits to the second memory. The second bits are retrieved from the second memory and at least the second bits are stored into the group of storage elements during a second write stage.

Abstract: A storage module and method for regulating garbage collection operations based on write activity of a host are disclosed. In one embodiment, a storage module determines whether the host is operating in a burst mode by determining whether write activity of the host over a time period exceeds a threshold. The write activity can comprise one or both of (i) an amount of data received from the host to be written in the storage module and (ii) a number of write commands received from the host. If the host is operating in the burst mode, the storage module limits an amount of garbage collection operations during the burst mode. When the host is no longer operating in the burst mode, the storage module increases an amount of garbage collection operations.

Abstract: A data storage device includes a controller coupled to a non-volatile memory having a three-dimensional (3D) configuration. The non-volatile memory includes a group of storage elements. Each storage element is configured to store multiple data bits. Data is sent from the controller to the non-volatile memory and first bits corresponding to a first portion of the data are stored into the group of storage elements during a first write stage. Each storage element of the group of storage elements stores at least one bit of the first bits upon completion of the first write stage. Second bits corresponding to a second portion of the data are sent to a second memory without sending the first bits to the second memory. The second bits are retrieved from the second memory and at least the second bits are stored into the group of storage elements during a second write stage.

Abstract: A mechanism is presented memory circuits, such a NAND-type flash memories, to autonomously protect themselves from temporary and short power drops. A detection mechanism looks for the supply voltage to drop below a function voltage for a period of time. When such an event occurs, a suspend mechanism is activated, and after completing the last micro-operation (such as a program pulse) the memory freezes. When power is again stable at an operational level, the suspended operation is resumed. The memory controller can then be notified upon occurrence of such voltage drop by polling a special status bit. Examples of how the pausing can be implemented include altering of clock signals and suspending sub-phases of larger operations.