Abstract: A method includes determining a first logical block address (LBA) range of a first set of data units of a first candidate block of the memory. The method also includes determining a second LBA range of a second set of data units of a relocation block of the memory. The method also includes determining that the first LBA range matches the second LBA range. The method further includes relocating first valid data of the first candidate block to the relocation block of the memory in response to determining that the first LBA range matches the second LBA range, where the first LBA range corresponds to multiple LBAs.

Abstract: A system and method is disclosed for fast secure destruction or erasure of data in a non-volatile memory. The method may include identifying a fast erase condition, such as an unauthorized access attempt, and then applying a fast erase process to a predetermined number of blocks of the non-volatile memory. The fast erase process may be implemented by applying an erase voltage for less than a full duration needed to place the blocks in a full erase state, but sufficient to make any data in those blocks unreadable. The system may include a non-volatile memory having a plurality of blocks and a controller configured to sequentially apply the erase voltage to a predetermined portion of the blocks for less than a time needed to fully erase those blocks such that the controller may rapidly make data unreadable without taking the full time to completely erase those blocks.

Abstract: A device includes a memory and a controller coupled to the memory. The controller is configured to maintain a first address translation table associated with the memory and a second address translation table associated with the memory. The controller is further configured to receive a command to erase the memory. The controller is further configured to switch an indicator of an active address translation table from the first address translation table to the second address translation table in response to receiving the command.

Abstract: A storage module and method for identifying hot and cold data are provided. The storage module can be removable from a host or can be embedded in a host. In one embodiment, a request to store data in a logical block address (LBA) of a memory of the storage module is received. A physical block associated with the LBA is determined, and it is also determined whether the physical block stores hot or cold data. A last-known open block is then selected, wherein the last-known open block is either hot or cold depending on whether the physical block stores hot or cold data. If space is available in the last-known open block, the data is written to the last-known open block.

Abstract: A storage device and method for reallocating storage device resources based on an estimated fill level of a host buffer are disclosed. In one embodiment, a storage device receives, from a host device, a rate at which the host device stores data in its buffer and tracks an amount of data that was received from the host device. The storage device estimates a fill level of the buffer at an elapsed time using the rate, the elapsed time, and the amount of data received from the host device over that elapsed time. If the estimated fill level of the buffer is above a threshold, the storage device increases a rate of receiving data from the host device.

Abstract: Systems, methods and/or devices are used to pair metablocks in a non-volatile storage device. In one aspect, a method of data organization of a memory device includes, writing data to and reading data from respective metablocks in a set of metablocks. The method further includes while performing said writing and reading: (1) accessing one or more management data structures in controller memory, identifying two or more metablock pairs; (2) accessing and updating metablock status information indicating which metablocks of the set of metablocks are closed, free and open; and (3) accessing and updating a valid count, corresponding to a number of sub-block memory units having valid data for each of a plurality of metablocks in the set of metablocks.

Abstract: Systems and methods for managing a data buffer of a non-volatile memory system are disclosed. The method may include a controller of a storage system retrieving host data, storing the retrieved data in a data buffer and transferring the data to a non-volatile memory. The controller may then overwrite the retrieved data in the data buffer as soon as the retrieved data has been transferred to the non-volatile memory die but prior to sending a command to program that data to the non-volatile memory array of the non-volatile memory. The system includes a non-volatile memory with a plurality of data latches and a non-volatile memory array, a data buffer and a controller configured to free the data buffer for receiving new data as soon as the prior data is transferred to the data latches and prior to any indication on success of programming prior data to the non-volatile memory array.

Abstract: An apparatus includes a memory storing a group of pages of data. An interface of the apparatus is configured to send, to a data storage device (DSD) from a first command queue, a first instruction of instructions to store the group of pages to the DSD using a logical address corresponding to the group of pages. The interface is further configured to send, to the DSD from a second command queue, a second instruction of the instructions to write the group of pages to the DSD using the logical address. Sending a first copy of the group of pages in association with the first instruction and sending a second copy of the group of pages in association with the second instruction enables a multi-stage programming operation to be performed at the DSD without storing the group of pages at the DSD between stages of the multi-stage programming operation.

Abstract: A memory system and method are provided for increasing read parallelism of translation pages. In one embodiment, a memory system is provided comprising a plurality of memory dies, where each memory die is configured with storage space for a portion of a logical-to-physical address map that is distributed among the plurality of memory dies. The memory system also comprises a controller in communication with the plurality of memory dies and configured to receive a plurality of requests to read a plurality of logical block addresses, determine which memory dies store portions of the logical-to-physical address map that contain the logical block addresses, and determine an order in which to read the portions of the logical-to-physical address map so that at least some of the portions that are stored in different memory dies are read in parallel. Other embodiments are provided.

Abstract: A method performed by a data storage device includes receiving, from a host device, a first instruction of a first set of instructions to write a first group of pages of data to a memory of the data storage device and receiving a second instruction of the first set of instructions to write the first group of pages of data. A first stage of a multi-stage programming operation is performed at a first physical address of the memory using a first copy of the first group of pages, and a second stage of the multi-stage programming operation is performed at the first physical address of the memory using a second copy of the first group of pages. The first copy and the second copy are received from the host device in association with the first instruction and the second instruction, respectively.

Abstract: A memory system and method are provided for performing garbage collection on blocks based on their obsolescence patterns. In one embodiment, a controller of a memory system classifies each of the plurality of blocks based on its obsolescence pattern and performs garbage collection only on blocks classified with similar obsolescence patterns. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.

Abstract: A storage module and method for regulating garbage collection operations based on write activity of a host are disclosed. In one embodiment, a storage module determines whether the host is operating in a burst mode by determining whether write activity of the host over a time period exceeds a threshold. The write activity can comprise one or both of (i) an amount of data received from the host to be written in the storage module and (ii) a number of write commands received from the host. If the host is operating in the burst mode, the storage module limits an amount of garbage collection operations during the burst mode. When the host is no longer operating in the burst mode, the storage module increases an amount of garbage collection operations.

Abstract: A method that may be performed by a data storage device includes configuring the data storage device to use a first scheduling scheme and, in response to detecting a trigger event, configuring the data storage device to use a second scheduling scheme. One of the first scheduling scheme and the second scheduling scheme is used to schedule performance of memory operations having the same operation type at a plurality of dies of a memory of the data storage device. The other of the first scheduling scheme and the second scheduling scheme is used to schedule memory operations opportunistically.

Abstract: A device includes a schedule engine including a mode selection input. The schedule engine has an operating mode based on the mode selection input. The operating mode includes an opportunistic scheduling mode based on the mode selection input having a first value and a pipelined scheduling mode based on the mode selection input having a second value. The device further includes a buffer coupled to the schedule engine.

Abstract: A storage module and method for managing logical-to-physical address mapping are disclosed. In one embodiment, a storage module is provided comprising a memory having a plurality of wordlines and a controller. The controller is configured to use a logical-to-physical address map to convert a logical address to a physical address of a wordline. A plurality of logical addresses in the map point to a single wordline, and the single wordline contains both data associated with the plurality of logical addresses and information about where to find each of the plurality of logical addresses in the single wordline . Storing the information about where to find each of the plurality of logical addresses in the wordline itself avoids the delay and complexity of using a larger logical-to-physical address map or multiple maps.

Abstract: Systems and methods for detecting a file of a predetermined size or greater are disclosed. Files may be downloaded to a storage device via a data stream. The storage device may analyze one or more aspects of the data stream, such as throughput and consistency, in order to determine whether the file is of a predetermined size or greater. In response to determining that the data stream includes a file of at least a predetermined size, the storage device may take one or more actions. One action is to store part or all of the file in a hybrid block, which is a block in non-volatile memory that is accessed (e.g., programmed and/or erased) in a different way than its designation. For example, a block originally designated for multi-level cell (MLC) storage may be programmed for single-level cell (SLC) storage, which is quicker than for MLC. In this way, the storage device may be able to store the downloaded file, with a certain throughput and consistency, without loss of data.

Abstract: A storage module and method for adaptive burst mode are provided. In one embodiment, a storage module is provided comprising a memory and a controller. The controller is configured to receive a plurality of write commands from a host controller in communication with the storage module, store the plurality of write commands in a command queue in the storage module, and choose one of a plurality of burst modes in which to operate the memory based on how many write commands are stored in the command queue.

Abstract: A storage module and method are disclosed for determining whether to back-up a previously-written lower page of data before writing an upper page of data. In one embodiment, a storage module receives a command to write an upper page of data to memory cells that have already been programmed with a lower page of data. The storage module determines whether a command to protect the lower page of data was previously received. The storage module backs-up the lower page of data in another area of the memory before writing the upper page of data to the memory cells only if it is determined that the command to protect the lower page of data was previously received. The storage module then writes the upper page of data to the memory cells.

Abstract: Systems and methods for configuring, controlling and operating a non-volatile cache are disclosed. A host system may poll a memory system as to the memory system's configuration of its non-volatile cache. Further, the host system may configure the non-volatile cache on the memory system, such as the size of the non-volatile cache and the type of programming for the non-volatile cache (e.g., whether the non-volatile cache is programmed according to SLC or the type of TRIM used to program cells in the non-volatile cache). Moreover, responsive to a command from the host to size the non-volatile cache, the memory system may over or under provision the cache. Further, the host may control operation of the non-volatile cache, such as by sending selective flush commands.

Abstract: A method performed by a data storage device includes receiving, from a host device, a first instruction of a first set of instructions to write a first group of pages of data to a memory of the data storage device and receiving a second instruction of the first set of instructions to write the first group of pages of data. A first stage of a multi-stage programming operation is performed at a first physical address of the memory using a first copy of the first group of pages, and a second stage of the multi-stage programming operation is performed at the first physical address of the memory using a second copy of the first group of pages. The first copy and the second copy are received from the host device in association with the first instruction and the second instruction, respectively.