Patents by Inventor Amruthavalli P. Alur
Amruthavalli P. Alur has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20200185289Abstract: An apparatus is provided which comprises: a plurality of dielectric layers forming a substrate, a plurality of first conductive contacts on a first surface of the substrate, a cavity in the first surface of the substrate defining a second surface parallel to the first surface, a plurality of second conductive contacts on the second surface of the substrate, one or more integrated circuit die(s) coupled with the second conductive contacts, and mold material at least partially covering the one or more integrated circuit die(s) and the first conductive contacts. Other embodiments are also disclosed and claimed.Type: ApplicationFiled: December 27, 2016Publication date: June 11, 2020Applicant: Intel CorporationInventors: Mitul MODI, Robert L. SANKMAN, Debendra MALLIK, Ravindranath V. MAHAJAN, Amruthavalli P. ALUR, Yikang DENG, Eric J. LI
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Publication number: 20200066627Abstract: A microelectronics package comprises a substrate that comprises a dielectric and at least two conductor layers within the dielectric, and an inductor structure having a magnetic core at least partially within the dielectric and extending at least between a first conductor layer and a second conductor layer. The inductor structure comprises at least one conductor that extends horizontally at least partially within the magnetic core. The conductor extends in the z-direction within the magnetic core between the first conductor layer and the second conductor layer. One or more vias extend within the dielectric adjacent to the magnetic core between the first conductor layer and the second conductor layer. The conductor of the inductor has a length extending through the magnetic core that is greater than a width of the conductor.Type: ApplicationFiled: August 22, 2018Publication date: February 27, 2020Applicant: INTEL CORPORATIONInventors: Huong Do, Kaladhar Radhakrishnan, Krishna Bharath, Yikang Deng, Amruthavalli P. Alur
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Publication number: 20200066634Abstract: A microelectronics package comprising a substrate, the substrate comprising a dielectric and at least first and second conductor level within the dielectric, where the first and second conductor levels are separated by at least one dielectric layer. The microelectronics package comprises an inductor structure that comprises a magnetic core. The magnetic core is at least partially embedded within the dielectric. The inductor structure comprises a first trace in the first conductor level, a second trace in the second conductor level, and a via interconnect connecting the first and second traces. The first trace and the second trace extend at least partially within the magnetic core.Type: ApplicationFiled: August 21, 2018Publication date: February 27, 2020Applicant: Intel CorporationInventors: Huong Do, Kaladhar Radhakrishnan, Krishna Bharath, Yikang Deng, Amruthavalli P. Alur
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Patent number: 10494700Abstract: Microelectronic substrates having copper alloy conductive routes to reduce warpage due to differing coefficient of thermal expansion of the components used to form the microelectronic substrates. In one embodiment, the conductive routes of the microelectronic substrate may comprise an alloy of copper and an alloying metal of tungsten, molybdenum, or a combination thereof. In another embodiment, the conductive routes of the microelectronic substrate may comprise an alloy of copper, an alloying metal of tungsten, molybdenum, or a combination thereof, and a co-deposition metal of nickel, cobalt, iron, or a combination thereof. In still another embodiment, the copper alloy conductive routes may have copper concentrations which are graded therethrough, which may enable better pattern formation during a subtractive etching process used to form the copper alloy conductive routes.Type: GrantFiled: August 10, 2017Date of Patent: December 3, 2019Assignee: Intel CorporationInventors: Robert A. May, Sri Ranga Sai Boyapati, Amruthavalli P. Alur, Daniel N. Sobieski
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Publication number: 20170362684Abstract: Microelectronic substrates having copper alloy conductive routes to reduce warpage due to differing coefficient of thermal expansion of the components used to form the microelectronic substrates. In one embodiment, the conductive routes of the microelectronic substrate may comprise an alloy of copper and an alloying metal of tungsten, molybdenum, or a combination thereof. In another embodiment, the conductive routes of the microelectronic substrate may comprise an alloy of copper, an alloying metal of tungsten, molybdenum, or a combination thereof, and a co-deposition metal of nickel, cobalt, iron, or a combination thereof. In still another embodiment, the copper alloy conductive routes may have copper concentrations which are graded therethrough, which may enable better pattern formation during a subtractive etching process used to form the copper alloy conductive routes.Type: ApplicationFiled: August 10, 2017Publication date: December 21, 2017Applicant: INTEL CORPORATIONInventors: Robert A. May, Sri Ranga Sai Boyapati, Amruthavalli P. Alur, Daniel N. Sobieski
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Patent number: 9758845Abstract: Microelectronic substrates having copper alloy conductive routes to reduce warpage due to differing coefficient of thermal expansion of the components used to form the microelectronic substrates. In one embodiment, the conductive routes of the microelectronic substrate may comprise an alloy of copper and an alloying metal of tungsten, molybdenum, or a combination thereof. In another embodiment, the conductive routes of the microelectronic substrate may comprise an alloy of copper, an alloying metal of tungsten, molybdenum, or a combination thereof, and a co-deposition metal of nickel, cobalt, iron, or a combination thereof. In still another embodiment, the copper alloy conductive routes may have copper concentrations which are graded therethrough, which may enable better pattern formation during a subtractive etching process used to form the copper alloy conductive routes.Type: GrantFiled: December 9, 2014Date of Patent: September 12, 2017Assignee: Intel CorporationInventors: Robert A. May, Sri Ranga Sai Boyapati, Amruthavalli P. Alur, Daniel N. Sobieski
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Publication number: 20160183361Abstract: Microelectronic substrates having copper alloy conductive routes to reduce warpage due to differing coefficient of thermal expansion of the components used to form the microelectronic substrates. In one embodiment, the conductive routes of the microelectronic substrate may comprise an alloy of copper and an alloying metal of tungsten, molybdenum, or a combination thereof. In another embodiment, the conductive routes of the microelectronic substrate may comprise an alloy of copper, an alloying metal of tungsten, molybdenum, or a combination thereof, and a co-deposition metal of nickel, cobalt, iron, or a combination thereof. In still another embodiment, the copper alloy conductive routes may have copper concentrations which are graded therethrough, which may enable better pattern formation during a subtractive etching process used to form the copper alloy conductive routes.Type: ApplicationFiled: December 9, 2014Publication date: June 23, 2016Applicant: Intel CorporationInventors: Robert A May, Sri Ranga Sai Boyapati, Amruthavalli P. Alur, Daniel N. Sobieski
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Publication number: 20150255411Abstract: Embodiments of the present disclosure are directed towards die-to-die bonding and associated integrated circuit (IC) package configurations. In one embodiment, a package assembly includes a package substrate having a solder resist layer disposed on a first side and a second side disposed opposite to the first side, a first die mounted on the first side and having an active side that is electrically coupled with the package substrate by one or more first die-level interconnects and a second die bonded with the active side of the first die using one or more second die-level interconnects, wherein at least a portion of the second die is disposed in a cavity that extends into the solder resist layer. Other embodiments may be described and/or claimed.Type: ApplicationFiled: March 5, 2014Publication date: September 10, 2015Inventors: Omkar G. Karhade, Debendra Mallik, Ravindranath V. Mahajan, Amruthavalli P. Alur
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Publication number: 20140376195Abstract: Methods of forming coreless package structures comprising backside land side capacitors (LSC) and dual sided solder resist are described. Those methods and structures may include forming a nickel coating on a first and second side of a core, forming a conductive plating on the nickel coating, forming building up layers on the conductive plating to form two panels on the core, de-paneling the panels from the core to form two coreless substrates, forming a laminate on the first and second sides of the coreless substrates, and forming an LSC on a backside of the coreless substrates.Type: ApplicationFiled: June 25, 2013Publication date: December 25, 2014Inventors: Qinglei Zhang, Amruthavalli P. Alur
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Patent number: 8456016Abstract: A semiconductor package comprises a semiconductor substrate that may comprise a core. The core may comprise one or more materials selected from a group comprising ceramics and glass dielectrics. The package further comprises a set of one or more inner conductive elements that is provided on the core, a set of one or more outer conductive elements that is provided on an outer side of the substrate, and a semiconductor die to couple to the substrate via one or more of the outer conductive elements. Example materials for the core may comprise one or more from alumina, zirconia, carbides, nitrides, fused silica, quartz, sapphire, and Pyrex. A laser may be used to drill one or more plated through holes to couple an inner conductive element to an outer conductive element. A dielectric layer may be formed in the substrate to insulate an outer conductive element from the core or an inner conductive element.Type: GrantFiled: March 23, 2010Date of Patent: June 4, 2013Assignee: Intel CorporationInventors: Yonggang Li, Amruthavalli P. Alur, Devarajan Balaraman, Xiwang Qi, Charan K. Gurumurthy
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Patent number: 8142878Abstract: In one embodiment, a substrate includes a core material formed from a filler including aluminum trihydrate and a secondary filler material. The secondary filler material has a secondary decomposition reaction that occurs at a temperature higher than a reflow temperature reached during processing of the substrate, or the secondary filler traps water released at reflow temperature by aluminum trihydrate. Other embodiments are described and claimed.Type: GrantFiled: August 22, 2007Date of Patent: March 27, 2012Assignee: Intel CorporationInventors: Amruthavalli P. Alur, Omar J. Bchir
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Publication number: 20110135883Abstract: A method of manufacturing a substrate for a microelectronic device comprises providing a dielectric material (120, 220, 920) as a build-up layer of the substrate, applying a primer (140, 240, 940) to a surface (121, 221, 921) of the dielectric material, and forming an electrically conductive layer (150, 250, 950) over the primer. In another embodiment, the method comprises providing the dielectric material, forming the feature extending into the dielectric material, forming the electrically conductive layer over the dielectric material, applying the primer to a surface of the electrically conductive layer and attaching a dielectric layer (960) to the primer.Type: ApplicationFiled: February 17, 2011Publication date: June 9, 2011Inventors: Houssam Jomaa, Amruthavalli P. Alur, Dilan Seneviratne
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Patent number: 7909977Abstract: A method of manufacturing a substrate for a microelectronic device comprises providing a dielectric material (120, 220, 920) as a build-up layer of the substrate, applying a primer (140, 240, 940) to a surface (121, 221, 921) of the dielectric material, and forming an electrically conductive layer (150, 250, 950) over the primer. In another embodiment, the method comprises providing the dielectric material, forming the feature extending into the dielectric material, forming the electrically conductive layer over the dielectric material, applying the primer to a surface of the electrically conductive layer and attaching a dielectric layer (960) to the primer.Type: GrantFiled: March 27, 2008Date of Patent: March 22, 2011Assignee: Intel CorporationInventors: Houssam Jomaa, Amruthavalli P. Alur, Dilan Seneviratne
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Patent number: 7749900Abstract: A semiconductor package comprises a semiconductor substrate that may comprise a core. The core may comprise one or more materials selected from a group comprising ceramics and glass dielectrics. The package further comprises a set of one or more inner conductive elements that is provided on the core, a set of one or more outer conductive elements that is provided on an outer side of the substrate, and a semiconductor die to couple to the substrate via one or more of the outer conductive elements. Example materials for the core may comprise one or more from alumina, zirconia, carbides, nitrides, fused silica, quartz, sapphire, and Pyrex. A laser may be used to drill one or more plated through holes to couple an inner conductive element to an outer conductive element. A dielectric layer may be formed in the substrate to insulate an outer conductive element from the core or an inner conductive element.Type: GrantFiled: September 30, 2008Date of Patent: July 6, 2010Assignee: Intel CorporationInventors: Yonggang Li, Amruthavalli P. Alur, Devarajan Balaraman, Xiwang Qi, Charan K. Gurumurthy
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Publication number: 20100078805Abstract: A semiconductor package comprises a semiconductor substrate that may comprise a core. The core may comprise one or more materials selected from a group comprising ceramics and glass dielectrics. The package further comprises a set of one or more inner conductive elements that is provided on the core, a set of one or more outer conductive elements that is provided on an outer side of the substrate, and a semiconductor die to couple to the substrate via one or more of the outer conductive elements. Example materials for the core may comprise one or more from alumina, zirconia, carbides, nitrides, fused silica, quartz, sapphire, and Pyrex. A laser may be used to drill one or more plated through holes to couple an inner conductive element to an outer conductive element. A dielectric layer may be formed in the substrate to insulate an outer conductive element from the core or an inner conductive element.Type: ApplicationFiled: September 30, 2008Publication date: April 1, 2010Inventors: Yonggang Li, Amruthavalli P. Alur, Devarajan Balaraman, Xiwang Qi, Charan K. Gurumurthy
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Publication number: 20090246462Abstract: A method of manufacturing a substrate for a microelectronic device comprises providing a dielectric material (120, 220, 920) as a build-up layer of the substrate, applying a primer (140, 240, 940) to a surface (121, 221, 921) of the dielectric material, and forming an electrically conductive layer (150, 250, 950) over the primer. In another embodiment, the method comprises providing the dielectric material, forming the feature extending into the dielectric material, forming the electrically conductive layer over the dielectric material, applying the primer to a surface of the electrically conductive layer and attaching a dielectric layer (960) to the primer.Type: ApplicationFiled: March 27, 2008Publication date: October 1, 2009Inventors: Houssam Jomaa, Amruthavalli P. Alur, Dilan Seneviratne
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Publication number: 20090053466Abstract: In one embodiment, a substrate includes a core material formed from a filler including aluminum trihydrate and a secondary filler material. The secondary filler material has a secondary decomposition reaction that occurs at a temperature higher than a reflow temperature reached during processing of the substrate, or the secondary filler traps water released at reflow temperature by aluminum trihydrate. Other embodiments are described and claimed.Type: ApplicationFiled: August 22, 2007Publication date: February 26, 2009Inventors: Amruthavalli P. Alur, Omar J. Bchir