Abstract: A screen protector configured to be disposed on an attaching body on an electronic device in an attaching mode to correspondingly cover a display screen of the electronic device. The screen protector comprises a grating sheet and a first attaching member disposed vertically adjacent to each other side-by-side and coated between two outer cover films. The screen protector is disposed on the attaching body on the electronic device in an attaching mode through the attaching member, so that a viewing zone defined by the grating sheet correspondingly covers the display screen of the electronic device.

Abstract: A semiconductor structure comprises a substrate having a first well region of a first conductive type, a second well region of a second conductive type, and a junction between the first well region and the second well region. The first conductive type and the second conductive type are complementary. A plurality of first dummy structures and second dummy structures and at least a first active region are defined in the first well region by an isolation structure. The first dummy structures are adjacent to the junction and respectively comprise a first metal silicide region and a first doped region of the first conductive type and between the first metal silicide region and the first well region. The first dummy structures are between the second dummy structures and the junction. The second dummy structures respectively comprise a second metal silicide region that direct contacts the first well region.

Abstract: A network device including a main bridge, a first bridge, a controller, and an Ethernet port is provided. When the Ethernet port is connected to a mesh network, the processing unit performs the following steps: controlling the Ethernet port to transmit a first broadcast packet; when the Ethernet port receives a second broadcast packet, parsing the second broadcast packet to extract the packet path information to determine whether a path loop exists; determining, according to the Ethernet interface weight (EIW), the slave interface uplink weight (SIUW), and the master device weight (MW) carried by the first broadcast packet and the second broadcast packet, (1) whether the network device plays a master device role, (2) whether the bridge of the Ethernet port is set as the main bridge or the first bridge, and (3) whether the Ethernet port allows data transmission.

Abstract: A semiconductor structure is disclosed. The semiconductor structure includes a substrate, a first well region of a first conductive type and a second well region of a second conductive type disposed in the substrate. The first conductive type and the second conductive type are complementary. A plurality of first dummy structures are disposed in the first well region and arranged along a junction between the first well region and the second well region. The first dummy structures respectively include a first conductive region and a first doped region disposed between the first conductive region and the first doped region.

Abstract: Light device control circuit includes signal processor; control circuit including control signal source and active switch, active switch having output end thereof electrically connected to control input side of the signal processor through control bus; data synchronization circuit including data signal source and another set of active switches, and the output end of the another set of active switches being electrically connected to data input side of signal processor through data bus, signal processor forming electrical connection with signal connection circuit by data output side to form signal and command synchronization between data input side and data output side; and warning light control IC connected to warning lights and forming electrical connection with data bus outside data output side, and transmitting data, clock pulse and ID information from data output side, so that the starter and the receivers select one of the flash modes to flash the light.

Abstract: A device comprises a vertical transistor. The vertical transistor comprises a pillar structure, at least one gate electrode, and a dielectric material. The pillar structure comprises a source region, a drain region, and a channel region. The source region and the drain region each individually comprise at least one electrically conductive material configured to inhibit hydrogen permeation therethrough. The channel region comprises a semiconductive material vertically between the source region and the drain region. The at least one gate electrode laterally neighbors the channel region of the semiconductive structure. The dielectric material is laterally between the semiconductive structure and the at least one gate electrode. Additional devices, and related electronic systems and methods are also disclosed.

Abstract: Some embodiments include an integrated assembly which includes a base structure. The base structure includes a series of conductive structures which extend along a first direction. The conductive structures have steps which alternate with recessed regions along the first direction. Pillars of semiconductor material are over the steps. The semiconductor material includes at least one element selected from Group 13 of the periodic table in combination with at least one element selected from Group 16 of the periodic table. The semiconductor material may be semiconductor oxide in some applications. Some embodiments include methods of forming integrated assemblies.

Abstract: A vertical transistor comprises a top source/drain region, a bottom source/drain region, a channel region vertically between the top and bottom source/drain regions, and a gate operatively laterally-adjacent the channel region. The top source/drain region and the channel region have a top interface and the bottom source/drain region and the channel region have a bottom interface. The channel region is crystalline and has an average crystal grain size of its crystal grains that is less than 20 nanometers. The channel region at the top interface or at the bottom interface has greater horizontal texture than volume of the crystal grains in the channel region that is vertically between the crystal grains that are at the top and bottom interfaces. Other embodiments and aspects are disclosed.

Abstract: Some embodiments include a transistor having an active region containing semiconductor material. The semiconductor material includes at least one element selected from Group 13 of the periodic table in combination with at least one element selected from Group 16 of the periodic table. The active region has a first region, a third region offset from the first region, and a second region between the first and third regions. A gating structure is operatively adjacent to the second region. A first carrier-concentration-gradient is within the first region, and a second carrier-concentration-gradient is within the third region. Some embodiments include methods of forming integrated assemblies.

Abstract: A transistor comprises a first conductive contact, a heterogeneous channel comprising at least one oxide semiconductor material over the first conductive contact, a second conductive contact over the heterogeneous channel, and a gate electrode laterally neighboring the heterogeneous channel. A device, a method of forming a device, a memory device, and an electronic system are also described.

Abstract: Method of controlling warning lights to enter low power mode includes steps of: setting predetermined ID Number of warning lights as starter, and remaining ID numbers as receivers; warning light set as starter receiving start command from control bus through signal line, and sending data, clock pulse, and ID information from data bus, and choosing low power mode to flash; warning lights set as receivers obtaining data, clock pulse, and ID information from data bus through signal lines, and flash mode of receivers and starter flashing in low power mode, and active switch of control circuit that executes low power mode receiving low power command sent from starter and forming conductive state, and current-reducing resistor which is electrically connected to active switch reducing passing current to predetermined ratio, so that reduced current is transmitted to receivers and then starter executes low power mode and reduces brightness of warning lights.

Abstract: A method used in forming integrated circuitry comprises forming conductive material over a substrate. The conductive material is patterned into a conductive line that is horizontally longitudinally elongated. The conductive material is vertically recessed in longitudinally-spaced first regions of the conductive line to form longitudinally-spaced conductive pillars that individually are in individual longitudinally-spaced second regions that longitudinally-alternate with the longitudinally-spaced first regions along the conductive line. The conductive pillars project vertically relative to the conductive material in the longitudinally-spaced and vertically-recessed first regions of the conductive line. Electronic components are formed directly above the conductive pillars. Individual of the electronic components are directly electrically coupled to individual of the conductive pillars. Additional methods, including structure independent of method, are disclosed.

Abstract: An array of vertical transistors comprises spaced pillars of individual vertical transistors that individually comprise an upper source/drain region, a lower source/drain region, and a channel region vertically there-between. The upper source/drain region comprises a conductor oxide material in individual of the pillars. The channel region comprises an oxide semiconductor material in the individual pillars. The lower source/drain region comprises a first conductive oxide material in the individual pillars atop and directly against a second conductive oxide material in the individual pillars. Horizontally-elongated and spaced conductor lines individually interconnect a respective multiple of the vertical transistors in a column direction. The conductor lines individually comprise the second conductive oxide material atop and directly against metal material. The first conductive oxide material, the second conductive oxide material, and the metal material comprise different compositions relative one another.

Abstract: A method of detecting a biological sample includes the following steps. A magnetic sensor chip is provided, wherein the magnetic sensor chip includes a substrate and a magnetic sensing layer located on the substrate. Probes are connected to the magnetic sensor chip. A sample solution containing biological samples labeled with a first marker is provided on the magnetic sensor chip, so that the biological samples labeled with the first marker are hybridized with the probes. Magnetic beads labeled with a second marker are provided on the magnetic sensor chip, so that the magnetic beads labeled with the second marker are bound onto the biological samples labeled with the first marker. A signal sensed by the magnetic sensing layer is detected by a magnetic sensor.

Abstract: Some embodiments include an integrated assembly containing a first structure which includes one or more transition metals, and containing a second structure over the first structure. The second structure has a first region directly against the first structure and has a second region spaced from the first structure by a gap region. The second structure includes semiconductor material having at least one element selected from Group 13 of the periodic table in combination with at least one element selected from Groups 15 and 16 of the periodic table. An ionic compound is within the gap region. Some embodiments include a method of forming an integrated assembly.