Abstract: A chip bonding alignment structure includes a semiconductor chip, a metal layer, an etching stop layer, at least one metal bump, a dielectric barrier layer, a silicon oxide layer, and a silicon carbonitride layer. The metal layer is disposed on a bonding surface of the semiconductor chip and has a metal alignment pattern. The etching stop layer covers the bonding surface and the metal layer. The metal bump extends upward from the metal layer and penetrates through the etching stop layer. The dielectric barrier layer covers the etching stop layer and the metal bump. The silicon oxide layer covers the dielectric barrier layer. The silicon carbonitride layer covers the silicon oxide layer.

Abstract: Provided is a microsphere including a glass sphere core. The glass sphere core includes a first nuclide, a second nuclide and a diffusion region extending inwardly from an outer surface of the glass sphere core, with the second nuclide distributed in the diffusion region. The first nuclide and the second nuclide become radioactive after being activated by neutrons to produce radiations including ?-rays or ?-rays, or simultaneously ?-rays and ?-rays. A preparation method of a microsphere is also provided.

Abstract: A planar heating structure is disclosed. The planar heating structure includes a glass substrate layer, a nanometallic transparent conductive layer, and a first passivation layer. The nanometallic transparent conductive layer is disposed on the glass substrate layer and receives a voltage to generate heat energy. The first passivation layer is disposed on the nanometallic transparent conductive layer and completely covers the nanometallic transparent conductive layer.

Abstract: A package structure includes a leadframe, a semiconductor die and a plastic package material. The leadframe includes a die pad and a plurality of leads. The leads are disposed on four peripheral regions of the die pad, and each of the leads includes a main body, at least one extending portion and a plurality of plating surfaces. The extending portion is connected to the main body, and the main body and the extending portion are integrally formed. The plating surfaces are disposed on the main body and the extending portion. The semiconductor die is disposed on the die pad of the leadframe. The plastic package material is disposed on the leadframe. The main body and the extending portion of each of the leads protrude a peripheral region of the plastic package material.

Abstract: An MRAM structure includes a dielectric layer. A first MRAM, a second MRAM and a third MRAM are disposed on the dielectric layer, wherein the second MRAM is disposed between the first MRAM and the third MRAM, and the second MRAM includes an MTJ. Two gaps are respectively disposed between the first MRAM and the second MRAM and between the second MRAM and the third MRAM. Two tensile stress pieces are respectively disposed in each of the two gaps. A first compressive stress layer surrounds and contacts the sidewall of the MTJ entirely. A second compressive stress layer covers the openings of each of the gaps and contacts the two tensile material pieces.

Abstract: A method for fabricating a semiconductor device includes the steps of first forming an aluminum (Al) pad on a substrate, forming a passivation layer on the substrate and an opening exposing the Al pad, forming a cobalt (Co) layer in the opening and on the Al pad, bonding a wire onto the Co layer, and then performing a thermal treatment process to form a Co—Pd alloy on the Al pad.

Abstract: A method for fabricating a semiconductor device includes the steps of: providing a substrate, wherein the substrate comprises a MRAM region and a logic region; forming a magnetic tunneling junction (MTJ) on the MRAM region; forming a top electrode on the MTJ; and then performing a flowable chemical vapor deposition (FCVD) process to form a first inter-metal dielectric (IMD) layer around the top electrode and the MTJ.

Abstract: An embodiment includes a semiconductor device, a plurality of fin structures extending from a substrate, the plurality of fin structures having a plurality of first fin structures and a plurality of second fin structures. The semiconductor device also includes a plurality of isolation regions on the substrate and disposed between the plurality of fin structures. The device also includes a plurality of gate structures on the plurality of isolation regions. The device also includes a plurality of epitaxy structures on one of the plurality of first fin structures. The device also includes a plurality of contact structures on the plurality of epitaxy structures, where the plurality of first fin structures, the plurality of gate structures, the plurality of epitaxy structures, and the plurality of contact structures are components of one or more resonators.

Abstract: A chip bonding alignment structure includes a semiconductor chip, a metal layer, an etching stop layer, at least one metal bump, a dielectric barrier layer, a silicon oxide layer, and a silicon carbonitride layer. The metal layer is disposed on a bonding surface of the semiconductor chip and has a metal alignment pattern. The etching stop layer covers the bonding surface and the metal layer. The metal bump extends upward from the metal layer and penetrates through the etching stop layer. The dielectric barrier layer covers the etching stop layer and the metal bump. The silicon oxide layer covers the dielectric barrier layer. The silicon carbonitride layer covers the silicon oxide layer.

Abstract: A memory device and a manufacturing method thereof are provided. The memory device includes a device substrate, a resistance variable layer and a top electrode. The bottom electrode is disposed on the device substrate. The resistance variable layer is disposed on the bottom electrode. The top electrode is disposed on the resistance variable layer. The bottom electrode is formed with a tensile stress, while the top electrode is formed with a compressive stress.

Abstract: A method for fabricating a semiconductor device includes the steps of first forming a magnetic tunneling junction (MTJ) on a substrate, forming a top electrode on the MTJ, forming an inter-metal dielectric (IMD) layer around the top electrode and the MTJ, forming a landing layer on the IMD layer and the MTJ, and then patterning the landing layer to form a landing pad. Preferably, the landing pad is disposed on the top electrode and the IMD layer adjacent to one side of the top electrode.

Abstract: A method of treating tunnel collapse includes leveling a collapse body and moving a pavilion support under the collapse cavity, lifting a shield plate until a lower edge of the shield plate surpasses a contour line of an initial supporting arch of a tunnel, connecting a bottom column and inserting a padding plate under a column. If the hydraulic prop retracts, the column, the bottom column, the padding plate and the hydraulic prop bear a load from the shield plate. Mounting and connecting the initial supporting arch, welding the intersection point of the column and the initial supporting arch, cutting off the column in the initial supporting arch. Transferring the load of the shield plate from the pavilion support to an initial supporting shed, spraying fast-setting concrete to a grid arch to form a closed shell, and pumping filling material to fill the space of the collapse cavity.

Abstract: A vehicle lighting device is provided. The vehicle lighting device includes a main body and a connecting unit. The main body has an upper film, a lower film, a light guide filler, and at least one lower light-emitting element. The upper film has a setting area and a light-permeable layer at a center of the setting area. A distance spaced apart between an edge of the light-permeable layer and an edge of the setting region is no more than 5 cm. The at least one lower light-emitting element is embedded in the light guide filler arranged between the lower film and the upper film and is located on a part of the setting region defined by orthogonally projecting the lower conductive layer onto the setting region. The connecting unit can electrically connect to a control circuit to control the at least one lower light-emitting element.

Abstract: A method for fabricating semiconductor device includes first forming a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate, performing an atomic layer deposition (ALD) process or a high-density plasma (HDP) process to form a passivation layer on the first MTJ and the second MTJ, performing an etching process to remove the passivation layer adjacent to the first MTJ and the second MTJ, and then forming an ultra low-k (ULK) dielectric layer on the passivation layer.

Abstract: A contextual label compression framework is presented that uses trained sequence to sequence models. A set of training data including received queries and related content can be processed to generate sequences of semantic encodings. These sequences can be used to train the sequence to sequence models, in order to be able to predict queries for instances of content when the relevant information for those instances is processed by the model. When such information is received for an instance, that information can be processed to generate a semantic encoding sequence which can then be processed by the model. A resulting semantic sequence output by the model can be segmented and decoded to produce a set of relevant queries for the instance of content. This information can then be provided to an entity associated with the instance of content for purposes in managing aspects relating to that content.

Abstract: A method of treating tunnel collapse includes mounting a shield plate, a column, a support column to form a combined support and moving the combined support onto an operation platform, lifting up the combined support, and enabling the height of canopy to be greater than the height of an initial supporting arch. Actively contacting a surface of a collapse cavity by a fixed support column and bearing a load, and lifting a movable support column to the top of the collapse cavity and bearing a load. Mounting an initial supporting arch, and welding the initial supporting arch with the support column. Removing a hydraulic prop after the support column contacting the initial supporting arch is cut off and the load of the shield plate is transferred to a supporting shed. Mounting an exhaust pipe and a filling material pumping pipe, and pumping a filling material into a collapse cavity space.

Abstract: An MRAM structure includes a dielectric layer. A first MRAM, a second MRAM and a third MRAM are disposed on the dielectric layer, wherein the second MRAM is disposed between the first MRAM and the third MRAM, and the second MRAM includes an MTJ. Two gaps are respectively disposed between the first MRAM and the second MRAM and between the second MRAM and the third MRAM. Two tensile stress pieces are respectively disposed in each of the two gaps. A first compressive stress layer surrounds and contacts the sidewall of the MTJ entirely. A second compressive stress layer covers the openings of each of the gaps and contacts the two tensile material pieces.

Abstract: A method of treating tunnel collapse includes leveling a collapse body and moving a pavilion support under the collapse cavity, lifting a shield plate until a lower edge of the shield plate surpasses a contour line of an initial supporting arch of a tunnel, connecting a bottom column and inserting a padding plate under a column. If the hydraulic prop retracts, the column, the bottom column, the padding plate and the hydraulic prop bear a load from the shield plate. Mounting and connecting the initial supporting arch, welding the intersection point of the column and the initial supporting arch, cutting off the column in the initial supporting arch. Transferring the load of the shield plate from the pavilion support to an initial supporting shed, spraying fast-setting concrete to a grid arch to form a closed shell, and pumping filling material to fill the space of the collapse cavity.

Abstract: A semiconductor device and method for forming the semiconductor device are provided. In some embodiments, a semiconductor substrate comprises a device region. An isolation structure extends laterally in a closed path to demarcate the device region. A first source/drain region and a second source/drain region are in the device region and laterally spaced. A sidewall of the first source/drain region directly contacts the isolation structure at a first isolation structure sidewall, and remaining sidewalls of the first source/drain region are spaced from the isolation structure. A selectively-conductive channel is in the device region, and extends laterally from the first source/drain region to the second source/drain region. A plate comprises a central portion and a first peripheral portion. The central portion overlies the selectively-conductive channel, and the first peripheral portion protrudes from the central portion towards the first isolation structure sidewall.

Abstract: In some embodiments, a semiconductor device is provided. The semiconductor device includes an isolation structure disposed in a semiconductor substrate, where an inner perimeter of the isolation structure demarcates a device region of the semiconductor substrate. A gate is disposed over the device region, where an outer perimeter of the gate is disposed within the inner perimeter of the isolation structure. A first source/drain region is disposed in the device region and on a first side of the gate. A second source/drain region is disposed in the device region and on a second side of the gate opposite the first side. A silicide blocking structure partially covers the gate, partially covers the first source/drain region, and partially covers the isolation structure, where a first sidewall of the silicide blocking structure is disposed between first opposite sidewalls of the gate.