Patents by Inventor An-I Yeh

An-I Yeh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210371601
    Abstract: A method for forming a chitin film is provided. The method includes the following steps. In a step (a), a chitin suspension is prepared by adding chitin to water. In a step (b), physical forces are provided to process the chitin suspension, so that a mean particle diameter of the chitin is reduced. In a step (c), the chitin suspension is applied to a target, and the chitin film is formed after the chitin suspension is dried.
    Type: Application
    Filed: July 6, 2020
    Publication date: December 2, 2021
    Inventors: An-I Yeh, Hsuan-Lun Chi
  • Patent number: 11139252
    Abstract: A semiconductor package includes a semiconductor die, a plurality of conductive bumps, a shielding layer, an encapsulant and a redistribution layer. The semiconductor die has an active surface, a backside surface and a lateral surface. The conductive bumps are disposed on the active surface of the semiconductor die. The shielding layer is disposed on the lateral surface of the semiconductor die. The encapsulant covers the shielding layer, and has a first surface and a second surface opposite to the first surface. The redistribution layer is disposed on the first surface of the encapsulant and electrically connected to the semiconductor die through the conductive bumps. The shielding layer is electrically connected to the redistribution layer.
    Type: Grant
    Filed: February 26, 2020
    Date of Patent: October 5, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Hsu-Nan Fang, Chun-Jun Zhuang, Yung I. Yeh
  • Patent number: 11081473
    Abstract: A semiconductor device package includes a first substrate, a dielectric layer, a thin film transistor (TFT) and an electronic component. The first substrate has a first surface and a second surface opposite to the first surface. The dielectric layer is disposed on the first surface of the first substrate. The dielectric layer has a first surface facing away from the first substrate and a second surface opposite to the first surface. The TFT layer is disposed on the dielectric layer. The electronic component is disposed on the second surface of the first substrate. A roughness of the first surface of the dielectric layer is less than a roughness of the first surface of the first substrate.
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: August 3, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Ming-Hung Chen, Sheng-Yu Chen, Chang-Lin Yeh, Yung-I Yeh
  • Publication number: 20210159188
    Abstract: A package structure includes a wiring structure, a first electronic device, a second electronic device, a protection material and a reinforcement structure. The first electronic device and the second electronic device are electrically connected to the wiring structure. The protection material is disposed between the first electronic device and the wiring structure and between the second electronic device and the wiring structure. The reinforcement structure is disposed on and contacts the first electronic device and the second electronic device. The reinforcement structure contacts the protection material.
    Type: Application
    Filed: November 22, 2019
    Publication date: May 27, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Hsu-Nan FANG, Yung-I YEH
  • Publication number: 20210118826
    Abstract: An electronic device includes a substrate, a transistor, and a ring resonator. The transistor is over the substrate. The transistor is configured to generate a quantum dot. The ring resonator is over the substrate and includes a conductive loop and an impedance matching element. The conductive loop overlaps with the transistor. The impedance matching element is on the conductive loop and is configured to determine a resonance frequency of the ring resonator.
    Type: Application
    Filed: October 17, 2019
    Publication date: April 22, 2021
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Shih-Yuan CHEN, Jiun-Yun LI, Rui-Fu XU, Chiung-Yu CHEN, Ting-I YEH, Yu-Jui WU, Yao-Chun CHANG
  • Publication number: 20210076510
    Abstract: A semiconductor device package includes a display device, an encapsulation layer disposed in direct contact with the display device, and a reinforced structure surrounded by the encapsulation layer. The reinforced structure is spaced apart from a surface of the display device. A method of manufacturing a semiconductor device package is also disclosed.
    Type: Application
    Filed: September 6, 2019
    Publication date: March 11, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Ming-Hung CHEN, Yung I. YEH, Chang-Lin YEH, Sheng-Yu CHEN
  • Publication number: 20210066354
    Abstract: A semiconductor device package includes a main substrate, at least one thin film transistor (TFT) module, at least one first electronic component, at least one encapsulant and a plurality of light emitting devices. The main substrate has a first surface and a second surface opposite to the first surface. The thin film transistor (TFT) module is disposed adjacent to and electrically connected to the first surface of the main substrate. The first electronic component is disposed adjacent to and electrically connected to the first surface of the main substrate. The encapsulant covers the at least one thin film transistor (TFT) module and the at least one first electronic component. The light emitting devices are electrically connected to the at least one thin film transistor (TFT) module.
    Type: Application
    Filed: August 30, 2019
    Publication date: March 4, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Ming-Hung CHEN, Yung I. YEH, Chang-Lin YEH, Sheng-Yu CHEN
  • Publication number: 20210057398
    Abstract: A semiconductor device package includes a first substrate, a dielectric layer, a thin film transistor (TFT) and an electronic component. The first substrate has a first surface and a second surface opposite to the first surface. The dielectric layer is disposed on the first surface of the first substrate. The dielectric layer has a first surface facing away from the first substrate and a second surface opposite to the first surface. The TFT layer is disposed on the dielectric layer. The electronic component is disposed on the second surface of the first substrate. A roughness of the first surface of the dielectric layer is less than a roughness of the first surface of the first substrate.
    Type: Application
    Filed: August 23, 2019
    Publication date: February 25, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Ming-Hung CHEN, Sheng-Yu CHEN, Chang-Lin YEH, Yung-I YEH
  • Publication number: 20210057572
    Abstract: A semiconductor device package includes a display device, an electronic module and a conductive adhesion layer. The display device includes a first substrate and a TFT layer. The first substrate has a first surface and a second surface opposite to the first surface. The TFT layer is disposed on the first surface of the first substrate. The electronic module includes a second substrate and an electronic component. The second substrate has a first surface facing the second surface of the first substrate and a second surface opposite to the first surface. The electronic component is disposed on the second surface of the second substrate. The conductive adhesion layer is disposed between the first substrate and the second substrate.
    Type: Application
    Filed: August 23, 2019
    Publication date: February 25, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Ming-Hung CHEN, Sheng-Yu CHEN, Chang-Lin YEH, Yung-I YEH
  • Patent number: 10913909
    Abstract: Systems and methods are provided for modifying or selecting processing conditions for bright stock formation based on compositional characterization of the feedstock and/or bright stock products. In some aspects, the compositional information can include Z-class characterization of the components of a feed and/or bright stock product, optionally in combination with carbon number and/or molecular weight for the components. The compositional information can be used to select processing conditions to allow for removal and/or modification of selected components within a bright stock in order to improve throughput and/or provide desirable cold flow properties.
    Type: Grant
    Filed: December 9, 2019
    Date of Patent: February 9, 2021
    Assignee: ExxonMobil Research and Engineering Company
    Inventors: Liezhong Gong, Helen S. Wellons, Kuangnan Qian, Lisa I. Yeh, James W. Gleeson
  • Patent number: 10797022
    Abstract: A semiconductor device package includes a first redistribution layer (RDL), a first die, a second die, a second RDL and an encapsulant. The first die is disposed on the first RDL and is electrically connected to the first RDL. The first die has a first electrical contact. The second die is disposed on the first RDL and is electrically connected to the first RDL. The second die has a first electrical contact. The second RDL is surrounded by the first RDL. The second RDL has a first electrical contact electrically connected to the first electrical contact of the first die and a second electrical contact electrically connected to the first electrical contact of the second die. A size of the first electrical contact of the second RDL is greater than a size of the second electrical contact of the second RDL.
    Type: Grant
    Filed: October 4, 2018
    Date of Patent: October 6, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Hsu-Nan Fang, Chun-Jun Zhuang, Yung I. Yeh, Ming-Chiang Lee
  • Publication number: 20200268792
    Abstract: Disclosed herein is a method for treating an inflammatory disease in a subject, including administering to the subject a therapeutically effective amount of a dihydrolipoic acid (DHLA) coated gold nanocluster about 0.1 to 20 nm in diameter. Also disclosed is a method for reducing the expression of a pro-inflammatory molecule in a cultured cell, including contacting the cultured cell with the said DHLA coated gold nanocluster. Still disclosed is a pharmaceutical composition that includes the present DHLA coated gold nanocluster. The pharmaceutical composition is useful for treating the inflammatory disease in the subject.
    Type: Application
    Filed: February 25, 2020
    Publication date: August 27, 2020
    Applicants: MacKay Memorial Hospital, GoldRed NanoBiotech CO., LTD.
    Inventors: Hsueh-Hsiao WANG, Hung-I YEH, Hong-Shong CHANG
  • Patent number: 10754566
    Abstract: A data storage device utilized for storing a plurality of data includes a memory and a controller. The memory includes a plurality of blocks, and each of the blocks includes a plurality of physical pages. The controller is coupled to the memory. When the data storage device is initiated, or when the data size read by a host is greater than a threshold value, the controller inspects the status of the data stored by the physical pages of the memory.
    Type: Grant
    Filed: June 19, 2017
    Date of Patent: August 25, 2020
    Assignee: SILICON MOTION, INC.
    Inventor: Szu-I Yeh
  • Publication number: 20200190415
    Abstract: Systems and methods are provided for modifying or selecting processing conditions for bright stock formation based on compositional characterization of the feedstock and/or bright stock products. In some aspects, the compositional information can include Z-class characterization of the components of a feed and/or bright stock product, optionally in combination with carbon number and/or molecular weight for the components. The compositional information can be used to select processing conditions to allow for removal and/or modification of selected components within a bright stock in order to improve throughput and/or provide desirable cold flow properties.
    Type: Application
    Filed: December 9, 2019
    Publication date: June 18, 2020
    Inventors: Liezhong Gong, Helen S. Wellons, Kuangnan Qian, Lisa I. Yeh, James W. Gleeson
  • Publication number: 20200194383
    Abstract: A semiconductor package includes a semiconductor die, a plurality of conductive bumps, a shielding layer, an encapsulant and a redistribution layer. The semiconductor die has an active surface, a backside surface and a lateral surface. The conductive bumps are disposed on the active surface of the semiconductor die. The shielding layer is disposed on the lateral surface of the semiconductor die. The encapsulant covers the shielding layer, and has a first surface and a second surface opposite to the first surface. The redistribution layer is disposed on the first surface of the encapsulant and electrically connected to the semiconductor die through the conductive bumps. The shielding layer is electrically connected to the redistribution layer.
    Type: Application
    Filed: February 26, 2020
    Publication date: June 18, 2020
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Hsu-Nan FANG, Chun-Jun ZHUANG, Yung I. YEH
  • Patent number: 10593630
    Abstract: A semiconductor package includes a semiconductor die, a plurality of conductive bumps, a shielding layer, an encapsulant and a redistribution layer. The semiconductor die has an active surface, a backside surface and a lateral surface. The conductive bumps are disposed on the active surface of the semiconductor die. The shielding layer is disposed on the lateral surface of the semiconductor die. The encapsulant covers the shielding layer, and has a first surface and a second surface opposite to the first surface. The redistribution layer is disposed on the first surface of the encapsulant and electrically connected to the semiconductor die through the conductive bumps. The shielding layer is electrically connected to the redistribution layer.
    Type: Grant
    Filed: May 11, 2018
    Date of Patent: March 17, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Hsu-Nan Fang, Chun-Jun Zhuang, Yung I. Yeh
  • Publication number: 20200083132
    Abstract: A semiconductor device package includes a carrier and an encapsulant disposed on the carrier. At least one portion of the encapsulant is spaced from the carrier by a space.
    Type: Application
    Filed: May 10, 2019
    Publication date: March 12, 2020
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Yen-Chi HUANG, Hao-Chih HSIEH, Jin Han SHIH, Yung I. YEH, Tun-Ching PI
  • Publication number: 20190348371
    Abstract: A semiconductor package includes a semiconductor die, a plurality of conductive bumps, a shielding layer, an encapsulant and a redistribution layer. The semiconductor die has an active surface, a backside surface and a lateral surface. The conductive bumps are disposed on the active surface of the semiconductor die. The shielding layer is disposed on the lateral surface of the semiconductor die. The encapsulant covers the shielding layer, and has a first surface and a second surface opposite to the first surface. The redistribution layer is disposed on the first surface of the encapsulant and electrically connected to the semiconductor die through the conductive bumps. The shielding layer is electrically connected to the redistribution layer.
    Type: Application
    Filed: May 11, 2018
    Publication date: November 14, 2019
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Hsu-Nan FANG, Chun-Jun ZHUANG, Yung I. YEH
  • Publication number: 20190109117
    Abstract: A semiconductor device package includes a first redistribution layer (RDL), a first die, a second die, a second RDL and an encapsulant. The first die is disposed on the first RDL and is electrically connected to the first RDL. The first die has a first electrical contact. The second die is disposed on the first RDL and is electrically connected to the first RDL. The second die has a first electrical contact. The second RDL is surrounded by the first RDL. The second RDL has a first electrical contact electrically connected to the first electrical contact of the first die and a second electrical contact electrically connected to the first electrical contact of the second die. A size of the first electrical contact of the second RDL is greater than a size of the second electrical contact of the second RDL.
    Type: Application
    Filed: October 4, 2018
    Publication date: April 11, 2019
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Hsu-Nan Fang, Chun-Jun Zhuang, Yung I. Yeh, Ming-Chiang Lee
  • Patent number: 10248339
    Abstract: A data storage device utilized for storing a plurality of data includes a memory and a controller. The memory includes a plurality of blocks, and each of the blocks includes a plurality of physical pages. The controller is coupled to the memory and maps the logical pages to the physical pages of the memory. When the controller detects that a first logical page of the logical pages is a currently-used logical page, it detects whether or not the second logical page which belongs to the last logical page of the first logical page is a currently-used logical page in order to find what is truly the last currently-used logical page.
    Type: Grant
    Filed: June 15, 2017
    Date of Patent: April 2, 2019
    Assignee: SILICON MOTION, INC.
    Inventor: Szu-I Yeh