Patents by Inventor An-nan Chang
An-nan Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11312123Abstract: A vacuum lamination system includes a film supply assembly, a film collection assembly, a lower lamination body, an upper lamination body, an air extractor, a moving assembly and a cutting assembly. The lower lamination body includes a first casing base and a lower heating assembly vertically movable and disposed in the first casing base. The lower heating assembly carries and moves the substrate so that the substrate is substantially flush with a top surface of the first casing base or retracted into the first casing base. The upper lamination body is vertically movable and disposed above the lower lamination body and includes an upper casing and an upper heating assembly disposed on the upper casing. The air extractor is connected to the lower lamination body. The moving assembly changes a height of a portion of the film. The cutting assembly cuts a portion of the film laminated onto the substrate.Type: GrantFiled: July 8, 2020Date of Patent: April 26, 2022Assignee: ELEADTK CO., LTD.Inventors: Ching-Nan Chang, Sheng-Yu Lin, Ming-Chan Chen
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Patent number: 11301326Abstract: A method and apparatus for performing dynamic recovery management regarding a RAID are provided. The method includes: writing a first set of protected data into a first protected access unit of multiple protected access units of the RAID, and recording a first set of management information corresponding to the first set of protected data, for data recovery of the first set of protected data; and when any storage device of multiple storage devices of the RAID malfunctions, writing a second set of protected data into a second protected access unit of the protected access units, and recording a second set of management information corresponding to the second set of protected data, for data recovery of the second set of protected data. Any set of the first set of protected data and the second set of protected data includes data and multiple parity-check codes.Type: GrantFiled: October 30, 2020Date of Patent: April 12, 2022Assignee: Silicon Motion, Inc.Inventor: An-Nan Chang
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Patent number: 11221773Abstract: A method and apparatus for performing mapping information management regarding a RAID are provided. The method includes: writing data into a data region of the RAID in a redirect-on-write (ROW) manner, and recording mapping information between logical addresses of the data and protected-access-unit addresses (p-addresses) of protected access units in the data region into a logical-address-to-p-address (L2p) table within a table region of the RAID; when partial data of the data is updated, maintaining an updating list including a set of L2p table entries for the partial data in a RAM, and maintaining a recovery log corresponding to the updating list in a log region of the RAID, for power failure recovery; and according to the updating list, detecting whether a number of same-location L2p table entries in the set of L2p table entries reaches a predetermined threshold, to selectively update the L2p table with the same-location L2p table entries.Type: GrantFiled: March 11, 2019Date of Patent: January 11, 2022Assignee: Silicon Motion, Inc.Inventor: An-Nan Chang
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Publication number: 20210384301Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a semiconductor strip structure over a semiconductor substrate. The semiconductor strip structure has a first doped region and a spacing region connected to the first doped region, and the spacing region is an undoped region. The method includes performing an implantation process over the first doped region and the spacing region to convert a first upper portion of the first doped region and a second upper portion of the spacing region into a continuous disorder region. The method includes forming a metal-semiconductor compound layer over the semiconductor strip structure to continuously cover the first doped region and the spacing region after the implantation process.Type: ApplicationFiled: August 23, 2021Publication date: December 9, 2021Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Gulbagh SINGH, Cheng-Yeh HUANG, Chin-Nan CHANG, Chih-Ming LEE, Chi-Yen LIN
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Publication number: 20210370657Abstract: A vacuum lamination system includes a film supply assembly, a film collection assembly, a lower lamination body, an upper lamination body, an air extractor, a moving assembly and a cutting assembly. The lower lamination body includes a first casing base and a lower heating assembly vertically movable and disposed in the first casing base. The lower heating assembly carries and moves the substrate so that the substrate is substantially flush with a top surface of the first casing base or retracted into the first casing base. The upper lamination body is vertically movable and disposed above the lower lamination body and includes an upper casing and an upper heating assembly disposed on the upper casing. The air extractor is connected to the lower lamination body. The moving assembly changes a height of a portion of the film. The cutting assembly cuts a portion of the film laminated onto the substrate.Type: ApplicationFiled: July 8, 2020Publication date: December 2, 2021Applicant: ELEADTK CO., LTD.Inventors: Ching-Nan Chang, Sheng-Yu Lin, Ming-Chan Chen
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Patent number: 11101354Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a semiconductor substrate. The method includes forming an isolation structure in the semiconductor substrate. The isolation structure surrounds a first active region of the semiconductor substrate. The method includes forming a semiconductor strip structure over the semiconductor substrate. The semiconductor strip structure extends across the first active region and extends over the isolation structure, the semiconductor strip structure has a first doped region and a spacing region connected to the first doped region, the first doped region extends across the first active region, the spacing region is over the isolation structure, and the spacing region is an undoped region. The method includes performing an implantation process over the spacing region. The method includes forming a metal silicide layer over the semiconductor strip structure to continuously cover the first doped region and the spacing region.Type: GrantFiled: August 3, 2020Date of Patent: August 24, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Gulbagh Singh, Cheng-Yeh Huang, Chin-Nan Chang, Chih-Ming Lee, Chi-Yen Lin
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Patent number: 11088136Abstract: A semiconductor device and method of forming the same are provided. The semiconductor device includes a substrate, a growth promoting region, a first gate stack, and a second gate stack. The substrate includes a first region and a second region. The growth promoting region is located in a surface of the substrate in the first region. The growth promoting region includes a first implantation species, and a surface of the substrate in the second region is free of the first implantation species. The first gate stack includes a first gate dielectric layer on the substrate in the first region. The second gate stack includes a second gate dielectric layer on the substrate in the second region.Type: GrantFiled: February 25, 2020Date of Patent: August 10, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Victor Chiang Liang, Chi-Feng Huang, Chia-Chung Chen, Chun-Pei Wu, Fu-Huan Tsai, Chung-Hao Chu, Chin-Nan Chang, Ching-Yu Yang, Ankush Chaudhary
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Patent number: 10991688Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a gate stack, a first doped region, a second doped region, and a buried doped region. The first doped region has a first conductivity type and is located in the substrate at a first side of the gate stack. The second doped region has the first conductivity type and is located in the substrate at a second side of the gate stack. The buried doped region has the first conductivity type and is buried in the substrate, extended from the first doped region to the second doped region, and separated from the gate stack by a distance.Type: GrantFiled: November 26, 2018Date of Patent: April 27, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Victor Chiang Liang, Chi-Feng Huang, Chia-Chung Chen, Chun-Pei Wu, Fu-Huan Tsai, Chung-Hao Chu, Chin-Nan Chang, Ching-Yu Yang, Ankush Chaudhary
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Patent number: 10956047Abstract: The instant disclosure provides an accelerated computer system and an accelerated method for writing data into discrete pages. The accelerated method includes executing write commands, with each write command including write data and a write address such that the write address corresponds to a write page of the first pages in a sector of a hard drive, identifying whether the write pages are successive according to the write addresses, acquiring stored data by reading the sector according to the write addresses if the write pages are discrete, writing the data stored in the first pages into the second pages of a memory, writing write data bit by bit into the second pages according to the write addresses, and writing the data stored in the second pages into the first pages.Type: GrantFiled: January 29, 2016Date of Patent: March 23, 2021Assignee: ACCELSTOR TECHNOLOGIES LTDInventors: Shih-Chiang Tsao, Ting-Fang Chien, An-Nan Chang
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Publication number: 20210073074Abstract: A method and apparatus for performing dynamic recovery management regarding a RAID are provided. The method includes: writing a first set of protected data into a first protected access unit of multiple protected access units of the RAID, and recording a first set of management information corresponding to the first set of protected data, for data recovery of the first set of protected data; and when any storage device of multiple storage devices of the RAID malfunctions, writing a second set of protected data into a second protected access unit of the protected access units, and recording a second set of management information corresponding to the second set of protected data, for data recovery of the second set of protected data. Any set of the first set of protected data and the second set of protected data includes data and multiple parity-check codes.Type: ApplicationFiled: October 30, 2020Publication date: March 11, 2021Inventor: An-Nan Chang
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Publication number: 20210045364Abstract: A smart aquaculture method is provided for an aquaculture system including a breeding pool, a feeding machine and a camera disposed in the breeding pool. The method includes: taking an underwater image by the camera; calculating a feed remaining amount according to the underwater image; and controlling the feeding machine according to the feed remaining amount to dispense feed to the breeding pool.Type: ApplicationFiled: October 1, 2019Publication date: February 18, 2021Inventors: Ing-Jer HUANG, Chin-Chang HUNG, Yun-Nan CHANG
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Patent number: 10860423Abstract: A method and apparatus for performing dynamic recovery management regarding a RAID are provided. The method includes: writing a first set of protected data into a first protected access unit of multiple protected access units of the RAID, and recording a first set of management information corresponding to the first set of protected data, for data recovery of the first set of protected data; and when any storage device of multiple storage devices of the RAID malfunctions, writing a second set of protected data into a second protected access unit of the protected access units, and recording a second set of management information corresponding to the second set of protected data, for data recovery of the second set of protected data. Any set of the first set of protected data and the second set of protected data includes data and multiple parity-check codes.Type: GrantFiled: July 16, 2019Date of Patent: December 8, 2020Assignee: Silicon Motion, Inc.Inventor: An-Nan Chang
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Publication number: 20200365696Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a semiconductor substrate. The method includes forming an isolation structure in the semiconductor substrate. The isolation structure surrounds a first active region of the semiconductor substrate. The method includes forming a semiconductor strip structure over the semiconductor substrate. The semiconductor strip structure extends across the first active region and extends over the isolation structure, the semiconductor strip structure has a first doped region and a spacing region connected to the first doped region, the first doped region extends across the first active region, the spacing region is over the isolation structure, and the spacing region is an undoped region. The method includes performing an implantation process over the spacing region. The method includes forming a metal silicide layer over the semiconductor strip structure to continuously cover the first doped region and the spacing region.Type: ApplicationFiled: August 3, 2020Publication date: November 19, 2020Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Gulbagh SINGH, Cheng-Yeh HUANG, Chin-Nan CHANG, Chih-Ming LEE, Chi-Yen LIN
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Patent number: 10734489Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a semiconductor substrate. The method includes forming an isolation structure in the semiconductor substrate. The isolation structure surrounds a first active region and a second active region of the semiconductor substrate. The method includes forming a semiconductor strip structure over the semiconductor substrate. The semiconductor strip structure extends across the first active region, the second active region, and the isolation structure between the first active region and the second active region, the semiconductor strip structure has a P-type doped region, an N-type doped region, and a spacing region. The method includes performing an implantation process over the spacing region. The method includes forming a metal silicide layer over the semiconductor strip structure to cover the P-type doped region, the N-type doped region, and the spacing region.Type: GrantFiled: November 2, 2018Date of Patent: August 4, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Gulbagh Singh, Cheng-Yeh Huang, Chin-Nan Chang, Chih-Ming Lee, Chi-Yen Lin
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Publication number: 20200210290Abstract: A method and apparatus for performing dynamic recovery management regarding a RAID are provided. The method includes: writing a first set of protected data into a first protected access unit of multiple protected access units of the RAID, and recording a first set of management information corresponding to the first set of protected data, for data recovery of the first set of protected data; and when any storage device of multiple storage devices of the RAID malfunctions, writing a second set of protected data into a second protected access unit of the protected access units, and recording a second set of management information corresponding to the second set of protected data, for data recovery of the second set of protected data. Any set of the first set of protected data and the second set of protected data includes data and multiple parity-check codes.Type: ApplicationFiled: July 16, 2019Publication date: July 2, 2020Inventor: An-Nan Chang
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Publication number: 20200194430Abstract: A semiconductor device and method of forming the same are provided. The semiconductor device includes a substrate, a growth promoting region, a first gate stack, and a second gate stack. The substrate includes a first region and a second region. The growth promoting region is located in a surface of the substrate in the first region. The growth promoting region includes a first implantation species, and a surface of the substrate in the second region is free of the first implantation species. The first gate stack includes a first gate dielectric layer on the substrate in the first region. The second gate stack includes a second gate dielectric layer on the substrate in the second region.Type: ApplicationFiled: February 25, 2020Publication date: June 18, 2020Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Victor Chiang Liang, Chi-Feng Huang, Chia-Chung Chen, Chun-Pei Wu, Fu-Huan Tsai, Chung-Hao Chu, Chin-Nan Chang, Ching-Yu Yang, Ankush Chaudhary
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Publication number: 20200150887Abstract: A method and apparatus for performing mapping information management regarding a RAID are provided. The method includes: writing data into a data region of the RAID in a redirect-on-write (ROW) manner, and recording mapping information between logical addresses of the data and protected-access-unit addresses (p-addresses) of protected access units in the data region into a logical-address-to-p-address (L2p) table within a table region of the RAID; when partial data of the data is updated, maintaining an updating list including a set of L2p table entries for the partial data in a RAM, and maintaining a recovery log corresponding to the updating list in a log region of the RAID, for power failure recovery; and according to the updating list, detecting whether a number of same-location L2p table entries in the set of L2p table entries reaches a predetermined threshold, to selectively update the L2p table with the same-location L2p table entries.Type: ApplicationFiled: March 11, 2019Publication date: May 14, 2020Inventor: An-Nan Chang
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Patent number: 10622351Abstract: Provided is a semiconductor device includes a gate stack, a first doped region, a second doped region, a first lightly doped region and a second lightly doped region. The gate stack is disposed on a substrate. The first doped region is located in the substrate at a first side of the gate stack. The second doped region is located in the substrate at a second side of the gate stack. The first lightly doped region is located in the substrate between the gate stack and the first doped region. The second lightly doped region is located in the substrate between the gate stack and the second doped region. A property of the first lightly doped region is different from a property of the second lightly doped region.Type: GrantFiled: November 26, 2018Date of Patent: April 14, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Victor Chiang Liang, Chi-Feng Huang, Chia-Chung Chen, Chun-Pei Wu, Fu-Huan Tsai, Chung-Hao Chu, Chin-Nan Chang, Ching-Yu Yang, Ankush Chaudhary
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Patent number: 10589831Abstract: A multi-axis aircraft with a wind resistant unit includes a fuselage having an upper face and a lower face. The fuselage includes a central axis passing through the upper face and the lower face. A plurality of rotors is mounted to the fuselage. Each rotor includes a rotating axis parallel to the central axis. A wind resistant unit includes a plurality of wind barriers disposed in a radial direction perpendicular to a reference axis. Each wind barrier includes a plurality of rods fixed by at least one fixing member. Two adjacent rods have a passage therebetween. Each rod includes an axis proximal end facing the reference axis and an axis remote end remote to the reference axis. Each wind barrier includes a coupling end and an airflow diversion end. The coupling end is fixed by at least one coupling member to the upper face of the fuselage.Type: GrantFiled: June 13, 2017Date of Patent: March 17, 2020Inventor: Nan-Chang Chiu
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Patent number: D900003Type: GrantFiled: August 15, 2019Date of Patent: October 27, 2020Inventor: Nan-Chang Chiu