Patents by Inventor An-nan Chang

An-nan Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200044035
    Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a semiconductor substrate. The method includes forming an isolation structure in the semiconductor substrate. The isolation structure surrounds a first active region and a second active region of the semiconductor substrate. The method includes forming a semiconductor strip structure over the semiconductor substrate. The semiconductor strip structure extends across the first active region, the second active region, and the isolation structure between the first active region and the second active region, the semiconductor strip structure has a P-type doped region, an N-type doped region, and a spacing region. The method includes performing an implantation process over the spacing region. The method includes forming a metal silicide layer over the semiconductor strip structure to cover the P-type doped region, the N-type doped region, and the spacing region.
    Type: Application
    Filed: November 2, 2018
    Publication date: February 6, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Gulbagh SINGH, Cheng-Yeh HUANG, Chin-Nan CHANG, Chih-Ming LEE, Chi-Yen LIN
  • Publication number: 20190343004
    Abstract: A method of forming a protective film on at least one electronic module is provided. The method includes the following steps. A protective material is disposed on at least one electronic module such that the protective material and the electronic modules are in contact with each other. The electronic modules and the protective material disposed on the electronic modules are disposed in a chamber, and a first ambient pressure is provided in the chamber. The protective material in the chamber is heated to a first temperature to soften the protective material disposed on the electronic modules. After the protective material is softened, a second ambient pressure greater than the first ambient pressure is provided in the chamber, wherein a gas in the chamber directly pressurizes the protective material such that the protective material conformally covers a top of the electronic modules.
    Type: Application
    Filed: April 25, 2019
    Publication date: November 7, 2019
    Applicant: ELEADTK CO., LTD.
    Inventors: Ching-Nan Chang, Sheng-Yu Lin, Ming-Chan Chen
  • Patent number: 10387047
    Abstract: A memory circuit includes a plurality of banks and a controller, each bank of the plurality of banks includes a plurality of segments, and each segment of the plurality of segments includes a plurality of bit lines and a plurality of word lines. A word line switch corresponding to a word line of a segment of the memory circuit is turned on and data are written into memory cells of the segment coupled to a plurality of bit lines of the segment and corresponding to the word line in turn after the controller enables an active command corresponding to the word line. When the controller enables at least one copy row write command, the data are simultaneously written into memory cells sharing a plurality of sense amplifiers with the plurality of bit lines of the segment and corresponding to at least one another word line.
    Type: Grant
    Filed: November 21, 2016
    Date of Patent: August 20, 2019
    Assignee: Etron Technology, Inc.
    Inventors: Chun Shiah, Cheng-Nan Chang, Yu-Hui Sung
  • Patent number: 10367887
    Abstract: A data storage system and a data storage method thereof are provided. The data storage system includes a first server and a second server. The first server is connected to a transmission line, and the first server includes a first data pool and a first controller. The first controller is configured to operate in an active mode. In the active mode, the first controller receives to-be-stored data from a client, stores the to-be-stored data in the first data pool, and sends first storage data through the transmission line. The second server is connected to the first server, and the second server includes a second data pool and a second controller. The second controller is configured to operate in the active mode. In the active mode, the second controller receives the to-be-stored data through the transmission line, and the second controller stores the to-be-stored data in the second data pool.
    Type: Grant
    Filed: December 27, 2016
    Date of Patent: July 30, 2019
    Assignee: ACCELSTOR LTD.
    Inventors: Chih-Kang Nung, Pao-Chien Li, An-Nan Chang, Shih-Chiang Tsao
  • Publication number: 20190109132
    Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a gate stack, a first doped region, a second doped region, and a buried doped region. The first doped region has a first conductivity type and is located in the substrate at a first side of the gate stack. The second doped region has the first conductivity type and is located in the substrate at a second side of the gate stack. The buried doped region has the first conductivity type and is buried in the substrate, extended from the first doped region to the second doped region, and separated from the gate stack by a distance.
    Type: Application
    Filed: November 26, 2018
    Publication date: April 11, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Victor Chiang Liang, Chi-Feng Huang, Chia-Chung Chen, Chun-Pei Wu, Fu-Huan Tsai, Chung-Hao Chu, Chin-Nan Chang, Ching-Yu Yang, Ankush Chaudhary
  • Publication number: 20190096881
    Abstract: Provided is a semiconductor device includes a gate stack, a first doped region, a second doped region, a first lightly doped region and a second lightly doped region. The gate stack is disposed on a substrate. The first doped region is located in the substrate at a first side of the gate stack. The second doped region is located in the substrate at a second side of the gate stack. The first lightly doped region is located in the substrate between the gate stack and the first doped region. The second lightly doped region is located in the substrate between the gate stack and the second doped region. A property of the first lightly doped region is different from a property of the second lightly doped region.
    Type: Application
    Filed: November 26, 2018
    Publication date: March 28, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Victor Chiang Liang, Chi-Feng Huang, Chia-Chung Chen, Chun-Pei Wu, Fu-Huan Tsai, Chung-Hao Chu, Chin-Nan Chang, Ching-Yu Yang, Ankush Chaudhary
  • Patent number: 10157916
    Abstract: Provided is a semiconductor device includes a gate stack, a first doped region, a second doped region, a first lightly doped region and a second lightly doped region. The gate stack is disposed on a substrate. The first doped region is located in the substrate at a first side of the gate stack. The second doped region is located in the substrate at a second side of the gate stack. The first lightly doped region is located in the substrate between the gate stack and the first doped region. The second lightly doped region is located in the substrate between the gate stack and the second doped region. A property of the first lightly doped region is different from a property of the second lightly doped region.
    Type: Grant
    Filed: April 10, 2017
    Date of Patent: December 18, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Victor Chiang Liang, Chi-Feng Huang, Chia-Chung Chen, Chun-Pei Wu, Fu-Huan Tsai, Chung-Hao Chu Chu, Chin-Nan Chang, Ching-Yu Yang, Ankush Chaudhary
  • Patent number: 10140047
    Abstract: The data storage system includes a memory, a hard disk, and a processing unit. A first logical address and a second logical address in a first logical block of the memory correspond to a piece of duplicated data, and the duplicated data is stored in two physical pages in the hard disk. When executing a de-duplication command, the processing unit transfers the duplicated data to a physical page mapped to a third logical address in a second logical block of the memory; the physical page has a third physical address, and the processing unit updates a first mapping relationship to make it provide a mapping relationship between the first logical address and the third logical address and a mapping relationship between the second logical address and the third logical address, and stores the mapping relationship between the third logical address and the third physical address in the memory.
    Type: Grant
    Filed: September 6, 2016
    Date of Patent: November 27, 2018
    Assignee: ACCELSTOR, INC.
    Inventors: Shih-Chiang Tsao, Ting-Fang Chien, An-Nan Chang
  • Patent number: 10127106
    Abstract: A redundant disk array system and a data storage method thereof are provided. The redundant disk array system includes a plurality of disks, a plurality of data stripes, and a processing unit. The processing unit stores, in a log manner into a write page, first logic page numbers corresponding to the pieces of write data, and records write locations of the first logic page numbers; the processing unit performs garbage collection on invalid page numbers of the first logic page numbers; and after executing garbage collection, the processing unit writes, in a log manner, second logic page numbers corresponding to the pieces of write data into the write pages traversed by a data stripe of the data stripes that has the most invalid page numbers, and records write locations of the second logic page numbers.
    Type: Grant
    Filed: July 7, 2016
    Date of Patent: November 13, 2018
    Assignee: ACCELSTOR LTD.
    Inventors: Shih-Chiang Tsao, Ting-Fang Chien, An-Nan Chang
  • Publication number: 20180294261
    Abstract: Provided is a semiconductor device includes a gate stack, a first doped region, a second doped region, a first lightly doped region and a second lightly doped region. The gate stack is disposed on a substrate. The first doped region is located in the substrate at a first side of the gate stack. The second doped region is located in the substrate at a second side of the gate stack. The first lightly doped region is located in the substrate between the gate stack and the first doped region. The second lightly doped region is located in the substrate between the gate stack and the second doped region. A property of the first lightly doped region is different from a property of the second lightly doped region.
    Type: Application
    Filed: April 10, 2017
    Publication date: October 11, 2018
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Victor Chiang Liang, Chi-Feng Huang, Chia-Chung Chen, Chun-Pei Wu, Fu-Huan Tsai, Chung-Hao Chu Chu, Chin-Nan Chang, Ching-Yu Yang, Ankush Chaudhary
  • Patent number: 10073771
    Abstract: A data storage method and a system thereof are disclosed. The data storage method includes allocating a first logical block and a second logical block, which are mapped to a physical block; the first logical block includes consecutive first logical pages, used to store logical addresses, and the second logical block includes consecutive second logical pages; on executing garbage collection, sequentially and consecutively storing valid logical addresses in second logical pages in the order of the second logical pages according to valid bits; and establishing a one-to-one second mapping relationship between the second logical pages and valid data pages according to the first mapping relationship.
    Type: Grant
    Filed: February 25, 2016
    Date of Patent: September 11, 2018
    Assignee: ACCELSTOR LTD.
    Inventors: Shih-Chiang Tsao, Ting-Fang Chien, An-Nan Chang
  • Patent number: 10073633
    Abstract: The present invention provides a data storage system and method. A controller is connected to a plurality of disk arrays, and each disk array is provided with a data protection unit for data protection. When one disk drive of one of the disk arrays is damaged, this disk array is defined as a damaged disk array, while other disk arrays without disk drives being damaged are defined as at least one normal disk array. The controller stops to write a new written data into the damaged disk array, while write the new written data into the normal disk arrays. The new written data will be protected by the data protection units of the normal disk arrays. Thereby, continuous data protection for the new written data by the data protection units together with preservation of storage performance of the system, after the disk drive is damaged, may be achieved.
    Type: Grant
    Filed: April 12, 2016
    Date of Patent: September 11, 2018
    Assignee: Accelstor Ltd.
    Inventors: Shih-Chiang Tsao, Ting-Fang Chien, An-Nan Chang
  • Patent number: 10037787
    Abstract: A circuit for outputting information of a memory circuit during a self-refresh mode includes a driver. The driver is coupled to a self-refresh control circuit and a self-refresh address counter. The driver is used for driving a plurality of pads of the memory circuit to output information of a plurality of inner signals corresponding to a self-refresh mode signal, and output information of addresses of a plurality of word lines of the memory circuit when the self-refresh mode signal and a test mode signal are enabled and the memory circuit enters the self-refresh mode. Each word line of the plurality of word lines corresponds to an inner signal of the plurality of inner signals.
    Type: Grant
    Filed: September 6, 2017
    Date of Patent: July 31, 2018
    Assignee: Etron Technology, Inc.
    Inventors: Chun Shiah, Ho-Yin Chen, Cheng-Nan Chang
  • Patent number: 10030075
    Abstract: Immunoglobulin chains or antibodies having light or heavy chain complementarity determining regions of antibodies that bind to P-Selectin Glycoprotein Ligand-1. Also disclosed are methods of inducing death of an activated T-cell and of modulating a T cell-mediated immune response in a subject.
    Type: Grant
    Filed: March 15, 2017
    Date of Patent: July 24, 2018
    Assignee: AbGenomics Cooperatief U.A.
    Inventors: Rong-Hwa Lin, Chung Nan Chang, Pei-Jiun Chen, Chiu-Chen Huang
  • Patent number: 10026620
    Abstract: The present invention relates to the growth of a native oxide layer on a surface of a silicon substrate. Deep ultraviolet (UV) light is irradiated to thereby effectively improve the quality of the native oxide layer. By improving the quality, the difficulty of the surface treatment of a cross-section sample for scanning capacitance microscopy (SCM) is improved. The life cycle and reliability of the sample are also improved with enhanced reproducibility for the measurement of SCM. Thus, the present invention provides an improved method and an apparatus using the same to prepare a cross-sectional sample for SCM. The feasibility and the concrete method for enhancing oxide layer quality on a silicon substrate surface by UV light irradiation under a humidity-controlled environment are established. The optimum parameters of irradiation time for n-type and p-type samples are made.
    Type: Grant
    Filed: June 22, 2017
    Date of Patent: July 17, 2018
    Assignee: NATIONAL APPLIED RESEARCH LABORATORIES
    Inventors: Mao-Nan Chang, Tsung-Yu Chan, Chia-Yi Wu, Chun-Ting Lin, Ming-Hua Shiao
  • Publication number: 20180152512
    Abstract: A data storage system and a data storage method thereof are provided. The data storage system includes a first server and a second server. The first server is connected to a transmission line, and the first server includes a first data pool and a first controller. The first controller is configured to operate in an active mode. In the active mode, the first controller receives to-be-stored data from a client, stores the to-be-stored data in the first data pool, and sends first storage data through the transmission line. The second server is connected to the first server, and the second server includes a second data pool and a second controller. The second controller is configured to operate in the active mode. In the active mode, the second controller receives the to-be-stored data through the transmission line, and the second controller stores the to-be-stored data in the second data pool.
    Type: Application
    Filed: December 27, 2016
    Publication date: May 31, 2018
    Inventors: CHIH-KANG NUNG, PAO-CHIEN LI, AN-NAN CHANG, SHIH-CHIANG TSAO
  • Publication number: 20180089768
    Abstract: A friend recommendation method includes the following operations: first clustering a target user to determine at least one initial to-be-recommended friend list where the target user is located according to several exercise time vectors, several exercise space vectors, and several exercise type vectors of a preset number of a plurality of users in a network; and second clustering the target user to determine a final to-be-recommended friend list where the target user is located according to an exercise intensity vector and an exercise effect vector of each of several users in the at least one initial to-be-recommended friend list.
    Type: Application
    Filed: September 22, 2017
    Publication date: March 29, 2018
    Inventors: Xiao-Long XU, Chao ZHOU, Ju-Nan CHANG
  • Publication number: 20180068693
    Abstract: A circuit for outputting information of a memory circuit during a self-refresh mode includes a driver. The driver is coupled to a self-refresh control circuit and a self-refresh address counter. The driver is used for driving a plurality of pads of the memory circuit to output information of a plurality of inner signals corresponding to a self-refresh mode signal, and output information of addresses of a plurality of word lines of the memory circuit when the self-refresh mode signal and a test mode signal are enabled and the memory circuit enters the self-refresh mode. Each word line of the plurality of word lines corresponds to an inner signal of the plurality of inner signals.
    Type: Application
    Filed: September 6, 2017
    Publication date: March 8, 2018
    Inventors: Chun Shiah, Ho-Yin Chen, Cheng-Nan Chang
  • Patent number: 9898216
    Abstract: The present invention relates to a data storage system and specific command execution method thereof, which is applied to a memory storage system. When a memory manager receives an command from a host system, it can judge whether the command is a normal command or a specific command. If the command is the specific command, read a first logic sector address, an accessible data length and a second logic sector address in the specific command, and duplicate the first logic sector address pointing to the physical storage address of the stored data reading to a memory buffer; and move physical storage address pointing to that from the first logic sector address to the second logic sector address. It can achieve both data reading and data moving by one specific command.
    Type: Grant
    Filed: December 11, 2015
    Date of Patent: February 20, 2018
    Assignee: Accelstor, Inc.
    Inventors: Shih-Chiang Tsao, Ting-Fang Chien, An-Nan Chang, Hann-Huei Chiou
  • Patent number: D839796
    Type: Grant
    Filed: March 7, 2017
    Date of Patent: February 5, 2019
    Inventor: Nan-Chang Chiu