Abstract: A communications circuit with an input port, a switching circuit coupled to the input port, and a first and second memory coupled to the switching circuit. The communications circuit also includes controlling circuitry adapted to operate the switching circuit to couple data received at the input port to the first memory while the second memory is disabled from power and to couple data received at the input port to the second memory once the first memory is filled with valid data.

Abstract: An example device includes an analog comparator circuitry having a first input configured to couple to an input voltage and a second input configured to couple to a reference voltage, the analog comparator circuitry configured to output a digital value corresponding to a difference between the input voltage and the reference voltage and output sampler circuitry configured to: produce a plurality of samples of the difference, and count the number of samples in which the input voltage is greater than the reference voltage. The example device also includes reference adaption circuitry configured to: determine, based on the count, whether to adjust the reference voltage; responsive to a determination to adjust the reference voltage, determine, based on the count, an amount of adjustment; and responsive to a determination not to adjust the reference voltage, provide an indication of the reference voltage to processor circuitry.

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed. An example apparatus includes interface circuitry to receive an analog signal. The example apparatus also includes sequencer circuitry to: determine whether the apparatus is to operate in a single transfer state or a multiple transfer state; access a configuration from a control register in a plurality of control registers; initiate a conversion of the analog signal to a digital value based on the configuration; and write the digital value to a result register in a plurality of result registers based on the determination.

Abstract: An example device includes an analog comparator circuitry having a first input configured to couple to an input voltage and a second input configured to couple to a reference voltage, the analog comparator circuitry configured to output a digital value corresponding to a difference between the input voltage and the reference voltage and output sampler circuitry configured to: produce a plurality of samples of the difference, and count the number of samples in which the input voltage is greater than the reference voltage. The example device also includes reference adaption circuitry configured to: determine, based on the count, whether to adjust the reference voltage; responsive to a determination to adjust the reference voltage, determine, based on the count, an amount of adjustment; and responsive to a determination not to adjust the reference voltage, provide an indication of the reference voltage to processor circuitry.

Abstract: A circuit with an interface, a transmit data register coupled to the interface, a storage device coupled to the transmit data register and including a plurality of storage locations, each storage location adapted to store a data unit, and a serial register coupled between the storage device and an output. The circuit also includes a CRC generation circuit having an input coupled between an output of the transmit data register and the storage device. The CRC generation circuit includes a first CRC generation block for providing a CRC in response to an X-bit data unit and an X-bit polynomial and a second CRC generation block with a collective X-bit input for providing a CRC in response to an X-bit data unit and a 2X-bit polynomial in a single clock cycle and a 2X-bit data unit and a 2X-bit polynomial in two clock cycles.

Abstract: A method is provided. In some examples, the method includes receiving, at a sequencer circuit of an analog-to-digital converter (ADC), a first request to perform a first conversion. In addition, the method includes determining, by the sequencer circuit, that the ADC is not busy. The method further includes responsive to determining that the ADC is not busy, and by the sequencer circuit, causing the ADC to perform the first conversion. The method also includes receiving, at the sequencer circuit, a second request to perform a second conversion. The method includes determining, by the sequencer circuit, that the ADC is busy and, responsive to determining that the ADC is busy, and by the sequencer circuit, waiting to cause the ADC to perform the second conversion.

Abstract: In an example, a method includes copying data between a source device and a destination device to form first copied data. The method also includes, responsive to completion of the copying, performing a verify-read operation. The verify-read operation includes determining a first checksum of the first copied data, copying the data between the source device and the destination device to form second copied data, determining a second checksum of the second copied data, comparing the first checksum to the second checksum to determine a comparison result, and determining a data integrity validation result based on the comparison result.

Abstract: A circuit with an interface, a transmit data register coupled to the interface, a storage device coupled to the transmit data register and including a plurality of storage locations, each storage location adapted to store a data unit, and a serial register coupled between the storage device and an output. The circuit also includes a CRC generation circuit having an input coupled between an output of the transmit data register and the storage device. The CRC generation circuit includes a first CRC generation block for providing a CRC in response to an X-bit data unit and an X-bit polynomial and a second CRC generation block with a collective X-bit input for providing a CRC in response to an X-bit data unit and a 2X-bit polynomial in a single clock cycle and a 2X-bit data unit and a 2X-bit polynomial in two clock cycles.

Abstract: In described examples, an integrated circuit (IC) includes a first temperature sensor, a processor, a second temperature sensor, and a reset module. The first sensor senses a first body temperature of the IC. The processor asserts a thermal shutdown signal if the first body temperature exceeds a first threshold. In response to the thermal shutdown signal, the second sensor asserts a reset request signal and senses a second body temperature of the IC. If the second body temperature is less than a second threshold, the second sensor asserts a reset end signal. The reset module outputs a system reset signal to the first sensor and the processor if the reset request signal is asserted, and outputs a system recovery signal if the reset end signal is asserted. The first sensor and the processor deactivate if the system reset signal is asserted, and activate if the system recovery signal is asserted.

Abstract: In an example, a method includes copying data between a source device and a destination device to form first copied data. The method also includes, responsive to completion of the copying, performing a verify-read operation. The verify-read operation includes determining a first checksum of the first copied data, copying the data between the source device and the destination device to form second copied data, determining a second checksum of the second copied data, comparing the first checksum to the second checksum to determine a comparison result, and determining a data integrity validation result based on the comparison result.

Abstract: A method is provided. In some examples, the method includes receiving, at a sequencer circuit of an analog-to-digital converter (ADC), a first request to perform a first conversion. In addition, the method includes determining, by the sequencer circuit, that the ADC is not busy. The method further includes responsive to determining that the ADC is not busy, and by the sequencer circuit, causing the ADC to perform the first conversion. The method also includes receiving, at the sequencer circuit, a second request to perform a second conversion. The method includes determining, by the sequencer circuit, that the ADC is busy and, responsive to determining that the ADC is busy, and by the sequencer circuit, waiting to cause the ADC to perform the second conversion.

Abstract: A communications circuit with an input port, a switching circuit coupled to the input port, and a first and second memory coupled to the switching circuit. The communications circuit also includes controlling circuitry adapted to operate the switching circuit to couple data received at the input port to the first memory while the second memory is disabled from power and to couple data received at the input port to the second memory once the first memory is filled with valid data.

Abstract: A system and method for dynamically protecting against security vulnerabilities in a reconfigurable signal chain. The system includes a signal chain formed from at least a first component connected with a second component. The first component has a set of source outputs and a first authentication block, and the second signal chain component has a set of destination inputs and a second authentication block. The system also includes a signal chain configurator that populates the first authentication block with at least one validated endpoint from the set of destination inputs. A signal chain integrity block, which is communicatively coupled with the first authentication block and the second authentication block, identifies a source-destination pair from one or more endpoint pairs formed from the at least one validated endpoint and the set of source outputs. The signal chain integrity block propagates the source-destination pair to the first authentication block and the second authentication block.

Abstract: An example apparatus includes clock divider circuitry configured to divide a system clock by a pre-scaler input to generate a divided clock; counter circuitry configured to increment a system count based on the divided clock; comparison circuitry configured to determine a count difference between the system count and a real-time clock count; and controller circuitry configured to modify the pre-scaler input based on a comparison of the count difference to a threshold value.

Abstract: A circuit includes a primary register region and a primary shadow register; a secondary register region and a secondary shadow register; and a safety controller having multiple states. The safety controller transitions to a first write state when a first write signal to write a first value to the primary register region is detected, and copies the first value written to the primary register region to the primary shadow register; transitions to a second write state when a second write signal to write a second value to the secondary register region is detected within a set amount of time of detection of the first write signal, and in the second write state, copies the second value written to the secondary register region to the secondary shadow register; transitions to a compare state to receive a comparison signal indicating whether the first value is the same as the second value; and transitions to an update state when the first value is the same as the second value.

Abstract: In described examples, an integrated circuit (IC) includes a first temperature sensor, a processor, a second temperature sensor, and a reset module. The first sensor senses a first body temperature of the IC. The processor asserts a thermal shutdown signal if the first body temperature exceeds a first threshold. In response to the thermal shutdown signal, the second sensor asserts a reset request signal and senses a second body temperature of the IC. If the second body temperature is less than a second threshold, the second sensor asserts a reset end signal. The reset module outputs a system reset signal to the first sensor and the processor if the reset request signal is asserted, and outputs a system recovery signal if the reset end signal is asserted. The first sensor and the processor deactivate if the system reset signal is asserted, and activate if the system recovery signal is asserted.

Abstract: In an example, a device includes a controller and a direct current (DC)-to-DC converter coupled to the controller and configured to provide a load current to a load. The device also includes a low-dropout (LDO) regulator coupled to the DC-to-DC converter. The controller includes digital logic, and the digital logic is configured to determine the load current. The digital logic is configured to turn on the LDO regulator if the load current is above a predetermined threshold. The digital logic is also configured to turn off the LDO regulator if the load current is below the predetermined threshold.

Abstract: A computing device, including a processor; a memory, wherein the memory is accessible for memory operations via a range of logical memory addresses; a peripheral interface including a first control register; and a peripheral address remapping module configured to determine that the peripheral interface is unused for interfacing with a peripheral; determine a first memory address for accessing the first control register; determine a first logical memory address, the first logical memory address outside of the range of logical memory addresses for accessing the memory; and map the first logical memory address to the first memory address, wherein the first control register is accessible for memory operations using the first logical memory address.

Abstract: This disclosure relates to a system that includes a centralized trim controller and a non-volatile memory that includes a trim sector configured for hosting trim data for one or more peripherals. The trim controller is configured to receive, for each of the one or more peripherals, trim values of the one or more peripherals from the trim sector of the nonvolatile memory, and provide the trim values to the one or more peripherals. Some trim values are updateable by receiving a password at the trim controller. If the password is valid, a timeout counter is initiated, during which time the trim value is updateable.

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed. An example apparatus includes interface circuitry to receive an analog signal. The example apparatus also includes sequencer circuitry to: determine whether the apparatus is to operate in a single transfer state or a multiple transfer state; access a configuration from a control register in a plurality of control registers; initiate a conversion of the analog signal to a digital value based on the configuration; and write the digital value to a result register in a plurality of result registers based on the determination.