Patents by Inventor Anand Kumar G
Anand Kumar G has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230132069Abstract: A circuit with an interface, a transmit data register coupled to the interface, a storage device coupled to the transmit data register and including a plurality of storage locations, each storage location adapted to store a data unit, and a serial register coupled between the storage device and an output. The circuit also includes a CRC generation circuit having an input coupled between an output of the transmit data register and the storage device. The CRC generation circuit includes a first CRC generation block for providing a CRC in response to an X-bit data unit and an X-bit polynomial and a second CRC generation block with a collective X-bit input for providing a CRC in response to an X-bit data unit and a 2X-bit polynomial in a single clock cycle and a 2X-bit data unit and a 2X-bit polynomial in two clock cycles.Type: ApplicationFiled: March 31, 2022Publication date: April 27, 2023Inventors: Robin Osa Hoel, Anand Kumar G, Dhivya Ravichandran, Aniruddha Periyapatna Nagendra
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Publication number: 20230113657Abstract: A circuit comprises a power controller, a real-time clock (RTC) sub-system, and a processing sub-system. The RTC sub-system includes an alarm register storing a predetermined time for a task, and provides an early warning countdown and a scheduled event signal. The processing sub-system includes a processor, a preemptive wakeup circuit, and a component coupled to the processor and configured to execute the task with the processor. The preemptive wakeup circuit comprises a selector logic circuit, a comparator, and a wakeup initiation circuit. The selector logic circuit receives latency values indicative of wakeup times for a clock generator and the component, and outputs a longest wakeup time to the comparator, which indicates when the early warning countdown and the longest wakeup time are equal. The wakeup initiation circuit generates a clock request and disables the sleep mode indicator. The power controller provides a clock signal and wakes the component.Type: ApplicationFiled: December 12, 2022Publication date: April 13, 2023Inventor: Anand Kumar G
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Publication number: 20230098382Abstract: A method is provided. In some examples, the method includes receiving, at a sequencer circuit of an analog-to-digital converter (ADC), a first request to perform a first conversion. In addition, the method includes determining, by the sequencer circuit, that the ADC is not busy. The method further includes responsive to determining that the ADC is not busy, and by the sequencer circuit, causing the ADC to perform the first conversion. The method also includes receiving, at the sequencer circuit, a second request to perform a second conversion. The method includes determining, by the sequencer circuit, that the ADC is busy and, responsive to determining that the ADC is busy, and by the sequencer circuit, waiting to cause the ADC to perform the second conversion.Type: ApplicationFiled: December 30, 2021Publication date: March 30, 2023Inventors: Anand Kumar G, Srinivasa BS Chakravarthy, Aniruddha Periyapatna Nagendra
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Publication number: 20230102099Abstract: This disclosure relates to an electronic device. The electronic device includes a non-transitory storage device, one or more peripherals, wherein the one or more peripherals are disabled, a processor configured to transmit a request to enable a peripheral of the one or more peripherals, and a power reset manager module. The power reset manager module is configured to receive the request to enable the peripheral. The power reset manager module includes a first memory configured to store, in response to the received request, an indication that peripheral was enabled. The processor is further configured to copy contents of the first memory to the non-transitory storage device and output the indication that the peripheral was enabled as a part of an update procedure.Type: ApplicationFiled: December 28, 2021Publication date: March 30, 2023Inventors: Veeramanikandan RAJU, Sudhakar SURENDRAN, Anand Kumar G
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Publication number: 20230097130Abstract: An integrated circuit includes an analog-to-digital converter (ADC) having selectable first and second analog channel inputs and a digital output. A window comparator coupled to the digital output. The window comparator configured to compare a digital value on the digital output to first and second threshold values. A programmable clock circuit configured to provide a clock signal to the ADC. A controller that, response to assertion of the trigger signal, is configured to generate a sample rate control signal to the clock circuit to cause the clock circuit to increase the frequency of the clock signal and toggle selection between the first and second analog channel inputs. A result comparison circuit having a comparison input coupled to the digital output. The result comparison circuit is configured to compare a first digital conversion output from the ADC toa second digital conversion output from the ADC.Type: ApplicationFiled: September 23, 2021Publication date: March 30, 2023Inventors: Veeramanikandan RAJU, Anand Kumar G
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Publication number: 20230091498Abstract: A computing device, including a processor; a memory, wherein the memory is accessible for memory operations via a range of logical memory addresses; a peripheral interface including a first control register; and a peripheral address remapping module configured to determine that the peripheral interface is unused for interfacing with a peripheral; determine a first memory address for accessing the first control register; determine a first logical memory address, the first logical memory address outside of the range of logical memory addresses for accessing the memory; and map the first logical memory address to the first memory address, wherein the first control register is accessible for memory operations using the first logical memory address.Type: ApplicationFiled: September 23, 2021Publication date: March 23, 2023Inventors: Veeramanikandan RAJU, Anand Kumar G, Prachi MISHRA
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Patent number: 11604709Abstract: Techniques including receiving a first control value, starting a timeout counter based on receiving the first control value, receiving a second control value, determining whether the second control value is received before the timeout counter expires, and based on the determination that the second control value is received before the timeout counter expires: determining whether the first control value is the same as the second control value, and loading the first control value into a set of control registers based on the determination that the first control value is the same as the second control value.Type: GrantFiled: August 23, 2021Date of Patent: March 14, 2023Assignee: Texas Instmments IncorporatedInventors: Veeramanikandan Raju, Anand Kumar G
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Patent number: 11606099Abstract: An integrated circuit includes an analog-to-digital converter (ADC) having selectable first and second analog channel inputs and a digital output. A window comparator coupled to the digital output. The window comparator configured to compare a digital value on the digital output to first and second threshold values. A programmable clock circuit configured to provide a clock signal to the ADC. A controller that, response to assertion of the trigger signal, is configured to generate a sample rate control signal to the clock circuit to cause the clock circuit to increase the frequency of the clock signal and toggle selection between the first and second analog channel inputs. A result comparison circuit having a comparison input coupled to the digital output. The result comparison circuit is configured to compare a first digital conversion output from the ADC to a second digital conversion output from the ADC.Type: GrantFiled: September 23, 2021Date of Patent: March 14, 2023Assignee: Texas Instruments IncorporatedInventors: Veeramanikandan Raju, Anand Kumar G
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Patent number: 11592484Abstract: A system and method for dynamically protecting against security vulnerabilities in a reconfigurable signal chain. The system includes a signal chain formed from at least a first component connected with a second component. The first component has a set of source outputs and a first authentication block, and the second signal chain component has a set of destination inputs and a second authentication block. The system also includes a signal chain configurator that populates the first authentication block with at least one validated endpoint from the set of destination inputs. A signal chain integrity block, which is communicatively coupled with the first authentication block and the second authentication block, identifies a source-destination pair from one or more endpoint pairs formed from the at least one validated endpoint and the set of source outputs. The signal chain integrity block propagates the source-destination pair to the first authentication block and the second authentication block.Type: GrantFiled: February 2, 2021Date of Patent: February 28, 2023Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Veeramanikandan Raju, Anand Kumar G, Christy Leigh She
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Patent number: 11567527Abstract: A circuit comprises a power controller, a real-time clock (RTC) sub-system, and a processing sub-system. The RTC sub-system includes an alarm register storing a predetermined time for a task, and provides an early warning countdown and a scheduled event signal. The processing sub-system includes a processor, a preemptive wakeup circuit, and a component coupled to the processor and configured to execute the task with the processor. The preemptive wakeup circuit comprises a selector logic circuit, a comparator, and a wakeup initiation circuit. The selector logic circuit receives latency values indicative of wakeup times for a clock generator and the component, and outputs a longest wakeup time to the comparator, which indicates when the early warning countdown and the longest wakeup time are equal. The wakeup initiation circuit generates a clock request and disables the sleep mode indicator. The power controller provides a clock signal and wakes the component.Type: GrantFiled: July 23, 2019Date of Patent: January 31, 2023Assignee: Texas Instruments IncorporatedInventor: Anand Kumar G
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Publication number: 20220412814Abstract: A temperature sensing device for a temperature-based tamper detection system includes an integrated circuit (IC) and a logic circuit. The logic circuit sends an enable signal to the IC, causing it to measure the device temperature, and initiates a security timer. In response to not receiving the device temperature before the security timer expires, the logic circuit outputs a tamper event signal and an error code. The logic circuit can disable the enable signal in response to not receiving the device temperature before the timer expires. In some implementations, the logic circuit is a first logic circuit, and the IC includes an analog integrated circuit (AIC) and a second logic circuit. The second logic circuit receives the enable signal from the first logic circuit, causes the AIC to measure the device temperature, and outputs a ready signal and the device temperature to the first logic circuit.Type: ApplicationFiled: June 23, 2021Publication date: December 29, 2022Inventor: Anand Kumar G
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Publication number: 20220342749Abstract: In an example, a method includes copying data between a source device and a destination device to form first copied data. The method also includes, responsive to completion of the copying, performing a verify-read operation. The verify-read operation includes determining a first checksum of the first copied data, copying the data between the source device and the destination device to form second copied data, determining a second checksum of the second copied data, comparing the first checksum to the second checksum to determine a comparison result, and determining a data integrity validation result based on the comparison result.Type: ApplicationFiled: July 16, 2021Publication date: October 27, 2022Inventor: Anand Kumar G
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Publication number: 20220269225Abstract: Techniques including receiving a first control value, starting a timeout counter based on receiving the first control value, receiving a second control value, determining whether the second control value is received before the timeout counter expires, and based on the determination that the second control value is received before the timeout counter expires: determining whether the first control value is the same as the second control value, and loading the first control value into a set of control registers based on the determination that the first control value is the same as the second control value.Type: ApplicationFiled: August 23, 2021Publication date: August 25, 2022Inventors: Veeramanikandan RAJU, Anand Kumar G
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Publication number: 20210156919Abstract: A system and method for dynamically protecting against security vulnerabilities in a reconfigurable signal chain. The system includes a signal chain formed from at least a first component connected with a second component. The first component has a set of source outputs and a first authentication block, and the second signal chain component has a set of destination inputs and a second authentication block. The system also includes a signal chain configurator that populates the first authentication block with at least one validated endpoint from the set of destination inputs. A signal chain integrity block, which is communicatively coupled with the first authentication block and the second authentication block, identifies a source-destination pair from one or more endpoint pairs formed from the at least one validated endpoint and the set of source outputs. The signal chain integrity block propagates the source-destination pair to the first authentication block and the second authentication block.Type: ApplicationFiled: February 2, 2021Publication date: May 27, 2021Inventors: Veeramanikandan Raju, Anand Kumar G, Christy Leigh She
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Patent number: 10935600Abstract: A system and method for dynamically protecting against security vulnerabilities in a reconfigurable signal chain. The system includes a signal chain formed from at least a first component connected with a second component. The first component has a set of source outputs and a first authentication block, and the second signal chain component has a set of destination inputs and a second authentication block. The system also includes a signal chain configurator that populates the first authentication block with at least one validated endpoint from the set of destination inputs. A signal chain integrity block, which is communicatively coupled with the first authentication block and the second authentication block, identifies a source-destination pair from one or more endpoint pairs formed from the at least one validated endpoint and the set of source outputs. The signal chain integrity block propagates the source-destination pair to the first authentication block and the second authentication block.Type: GrantFiled: April 5, 2019Date of Patent: March 2, 2021Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Veeramanikandan Raju, Anand Kumar G, Christy Leigh She
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Publication number: 20210026399Abstract: A circuit comprises a power controller, a real-time clock (RTC) sub-system, and a processing sub-system. The RTC sub-system includes an alarm register storing a predetermined time for a task, and provides an early warning countdown and a scheduled event signal. The processing sub-system includes a processor, a preemptive wakeup circuit, and a component coupled to the processor and configured to execute the task with the processor. The preemptive wakeup circuit comprises a selector logic circuit, a comparator, and a wakeup initiation circuit. The selector logic circuit receives latency values indicative of wakeup times for a clock generator and the component, and outputs a longest wakeup time to the comparator, which indicates when the early warning countdown and the longest wakeup time are equal. The wakeup initiation circuit generates a clock request and disables the sleep mode indicator. The power controller provides a clock signal and wakes the component.Type: ApplicationFiled: July 23, 2019Publication date: January 28, 2021Inventor: Anand Kumar G
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Publication number: 20200319250Abstract: A system and method for dynamically protecting against security vulnerabilities in a reconfigurable signal chain. The system includes a signal chain formed from at least a first component connected with a second component. The first component has a set of source outputs and a first authentication block, and the second signal chain component has a set of destination inputs and a second authentication block. The system also includes a signal chain configurator that populates the first authentication block with at least one validated endpoint from the set of destination inputs. A signal chain integrity block, which is communicatively coupled with the first authentication block and the second authentication block, identifies a source-destination pair from one or more endpoint pairs formed from the at least one validated endpoint and the set of source outputs. The signal chain integrity block propagates the source-destination pair to the first authentication block and the second authentication block.Type: ApplicationFiled: April 5, 2019Publication date: October 8, 2020Inventors: Veeramanikandan Raju, Anand Kumar G, Christy Leigh She