Patents by Inventor Anand Sharma

Anand Sharma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200150640
    Abstract: A computer implemented method includes turning off a sensor, receiving fall curve data from the sensor, and comparing the received fall curve data to a set of fall curve signatures to identify the sensor or a sensor fault.
    Type: Application
    Filed: November 13, 2018
    Publication date: May 14, 2020
    Inventors: Tusher Chakraborty, Akshay Uttama Nambi Srirangam Narashiman, Ranveer Chandra, Rahul Anand Sharma, Manohar Swaminathan, Zerina Kapetanovic, Jonathan Appavoo
  • Publication number: 20200106438
    Abstract: A circuit or associated system or method comprises a first driver including a first transistor bank and a first resistor connected in series between a first predetermined voltage and an output pad, the first transistor bank including a first driver transistor and a plurality of first calibration transistors, wherein the plurality of first calibration transistors are respectively controlled based on a combination of bits of a first calibration code and on an output of at least one first logic gate.
    Type: Application
    Filed: September 28, 2018
    Publication date: April 2, 2020
    Inventors: Shiv Harit Mathur, Anand Sharma
  • Publication number: 20190266015
    Abstract: Systems, methods, and computer-executable instructions for scheduling neural network workloads on an edge device. A performance model for each neural network model is received. Parameters for each neural network workload is determined based on an associated performance model. Processing core assignments are determined from a plurality of processing cores for each neural network workload based on the corresponding performance model and processing core utilization. Image streams are received and associated with a neural network workload. Each neural network workload is scheduled to run on the processing cores based on the processing core assignments.
    Type: Application
    Filed: February 27, 2018
    Publication date: August 29, 2019
    Inventors: Ranveer Chandra, Rahul Anand Sharma
  • Publication number: 20190204100
    Abstract: A method and a system for predicting traffic conditions of a geographical area are provided. A directed graph of a road network of the geographical area is generated. Position information, received from devices of corresponding vehicles that are traversing between road segments including at least first and second road segments, is located on the generated directed graph. Further, first and second times are determined based on the located position information on the generated directed graph. A traffic time of the first road segment is determined based on an average of time differences of the first and second times of each of the one or more first vehicles after filtering out a time period between the first and second times. The traffic conditions of the road network are predicted based on the determined traffic time of each of the road segments.
    Type: Application
    Filed: March 9, 2018
    Publication date: July 4, 2019
    Inventor: Anand Sharma
  • Publication number: 20190197132
    Abstract: A method and a system for location clustering for a transportation service are provided. A plurality of locations are clustered into a plurality of clusters, each having one or more locations of the plurality of locations. A graph is generated by connecting the plurality of clusters. A first cluster of the plurality of clusters is connected to one or more second clusters of the plurality of clusters that satisfy one or more threshold parameters. The graph is segmented into a plurality of fully-connected maximal sub-graphs based on one or more connections between the plurality of clusters. One or more fully-connected maximal sub-graphs of the plurality of fully-connected maximal sub-graphs have a set of common clusters. The plurality of fully-connected maximal sub-graphs are used for performing one or more transportation service operations of the transportation service.
    Type: Application
    Filed: March 8, 2018
    Publication date: June 27, 2019
    Inventors: Anand Sharma, Rajesh Kumar Singh, Shailesh Kumar, Kunal Sachdeva
  • Patent number: 10134728
    Abstract: An integrated circuit may include a plurality of input/output (I/O) cells used for communicating signals, power, and ground to and from a core of the integrated circuit. The I/O cells may each include a bond pad formed in one or more top metal layers. One or more of the bond pads may be offset a predetermined distance from an I/O cell edge corresponding to a chip edge of the integrated circuit. A volume may be determined by the I/O cell edge and the predetermined distance and one or more rails may be disposed in the volume and in at least one metal layer common with at least one metal layer of the bond pad. The rails may be involved in the discharge of electrostatic discharge (ESD) current, and may reduce path resistance of the path used to discharge the ESD current.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: November 20, 2018
    Assignee: SanDisk Technologies LLC
    Inventors: Shiv Harit Mathur, Anand Sharma, Lakhdar Iguelmamene, Richard J K Hong, Rajeswara Rao Bandaru
  • Patent number: 10129012
    Abstract: A non-source-synchronous system may include a clock-sending device and a clock-receiving device that communicate via a communications bus. The clock-sending device and the clock-receiving device may perform a tuning operation, in which the clock-receiving device sends one or more data signals on one or more data lines of the communications bus to the clock-sending device. The clock-sending device may delay its internal clock signal by an amount based on the one or more data signals. The clock-sending device may then perform sampling of data signals received from the clock-receiving device based on the tuning operation. The tuning operation may be performed in accordance with SDR or DDR, and thus allow for SDR or DDR communication with optimal sampling for systems that do not use a data strobe.
    Type: Grant
    Filed: March 29, 2017
    Date of Patent: November 13, 2018
    Assignee: SanDisk Technologies LLC
    Inventors: Krishnamurthy Dhakshinamurthy, Shajith Musaliar Sirajudeen, Jayaprakash Naradasi, Bhavin Odedara, Yosi Pinto, Rampraveen Somasundaram, Anand Sharma
  • Publication number: 20180302093
    Abstract: A circuit may receive control signals to generate an output signal with pulses corresponding to pulses of a source signal. The circuit may include a primary circuit and an auxiliary circuit. The primary circuit may constantly participate in the generation of pulses of the output signal. The auxiliary circuit may selectively participate with the primary circuit in the generation of the pulses. For two consecutive pulses of the output signal, whether the auxiliary circuit participates in generating the latter of the two pulses may depend on whether a threshold level is crossed during generation of the consecutive pulses.
    Type: Application
    Filed: June 19, 2017
    Publication date: October 18, 2018
    Applicant: SanDisk Technologies LLC
    Inventors: Shiv Harit Mathur, Anand Sharma, Ramakrishnan Karungulam Subramanian, Nitin Gupta
  • Patent number: 9996655
    Abstract: A design flow of an integrated circuit may include a skeleton input/output (I/O) generation stage during which information about ESD protection circuitry and rails but not functional circuitry of the I/O cells of the integrated circuit is generated. The information may be used in an ESD analysis stage to generate performance characteristics of the ESD protection circuitry. Results of the ESD analysis may then be used to design optimized ESD protection circuitry along with the rest of the circuit components of the I/O cells. In this way, the design of ESD protection circuitry may be optimized without having to redo a completed I/O cell design and significantly delay the design flow before tapeout.
    Type: Grant
    Filed: June 3, 2016
    Date of Patent: June 12, 2018
    Assignee: SanDisk Technologies LLC
    Inventors: Anand Sharma, Shiv Harit Mathur, Rajeswara Rao Bandaru
  • Publication number: 20180144288
    Abstract: An automated system for tracking inventory is provided. The automated system tracks the sufficiency of an inventory by the weight of the items composing the inventory so that resulting inventory deficiencies can be automatically sensed either continuously or periodically at predetermined polling intervals through container transducers coupled to a WIFI enabled microprocessor, wherein the microprocessor posts the weight-based output of the transducers to a cloud server that determines if the weight-based output signifies an inventory deficiency by comparing it to a predetermined threshold. A user may through their computer set the predetermined threshold and polling intervals. The user may also export the cloud server determinations in the form of alerts back to their computer or to registered user-suppliers for replenishing the deficient inventory.
    Type: Application
    Filed: November 23, 2016
    Publication date: May 24, 2018
    Inventors: Sajeed Sayed, Archana Kamath, Anand Sharma
  • Publication number: 20180083764
    Abstract: A non-source-synchronous system may include a clock-sending device and a clock-receiving device that communicate via a communications bus. The clock-sending device and the clock-receiving device may perform a tuning operation, in which the clock-receiving device sends one or more data signals on one or more data lines of the communications bus to the clock-sending device. The clock-sending device may delay its internal clock signal by an amount based on the one or more data signals. The clock-sending device may then perform sampling of data signals received from the clock-receiving device based on the tuning operation. The tuning operation may be performed in accordance with SDR or DDR, and thus allow for SDR or DDR communication with optimal sampling for systems that do not use a data strobe.
    Type: Application
    Filed: March 29, 2017
    Publication date: March 22, 2018
    Applicant: SanDisk Technologies LLC
    Inventors: Krishnamurthy Dhakshinamurthy, Shajith Musaliar Sirajudeen, Jayaprakash Naradasi, Bhavin Odedara, Yosi Pinto, Rampraveen Somasundaram, Anand Sharma
  • Patent number: 9799828
    Abstract: Topological insulators can be utilized in a new type of infrared photodetector that is intrinsically sensitive to the polarization of incident light and static magnetic fields. The detector isolates single topological insulator surfaces and allows light collection and exposure to static magnetic fields. The wavelength range of interest is between 750 nm and about 100 microns. This detector eliminates the need for external polarization selective optics. Polarization sensitive infrared photodetectors are useful for optoelectronics applications, such as light detection in environments with low visibility in the visible wavelength regime.
    Type: Grant
    Filed: October 3, 2016
    Date of Patent: October 24, 2017
    Assignee: National Technology & Engineering Solutions of Sandia, LLC
    Inventor: Peter Anand Sharma
  • Publication number: 20170255741
    Abstract: A design flow of an integrated circuit may include a skeleton input/output (I/O) generation stage during which information about ESD protection circuitry and rails but not functional circuitry of the I/O cells of the integrated circuit is generated. The information may be used in an ESD analysis stage to generate performance characteristics of the ESD protection circuitry. Results of the ESD analysis may then be used to design optimized ESD protection circuitry along with the rest of the circuit components of the I/O cells. In this way, the design of ESD protection circuitry may be optimized without having to redo a completed I/O cell design and significantly delay the design flow before tapeout.
    Type: Application
    Filed: June 3, 2016
    Publication date: September 7, 2017
    Applicant: SanDisk Technologies LLC
    Inventors: Anand Sharma, Shiv Harit Mathur, Rajeswara Rao Bandaru
  • Patent number: 9748345
    Abstract: Ion implantation or deposition can be used to modify the bulk electrical properties of topological insulators. More particularly, ion implantation or deposition can be used to compensate for the non-zero bulk conductivity due to extrinsic charge carriers. The direct implantation of deposition/annealing of dopants allows better control over carrier concentrations for the purposes of achieving low bulk conductivity. Ion implantation or deposition enables the fabrication of inhomogeneously doped structures, enabling new types of device designs.
    Type: Grant
    Filed: June 8, 2016
    Date of Patent: August 29, 2017
    Assignee: National Technology & Engineering Solutions of Sandia, LLC
    Inventor: Peter Anand Sharma
  • Publication number: 20170213817
    Abstract: An integrated circuit may include a plurality of input/output (I/O) cells used for communicating signals, power, and ground to and from a core of the integrated circuit. The I/O cells may each include a bond pad formed in one or more top metal layers. One or more of the bond pads may be offset a predetermined distance from an I/O cell edge corresponding to a chip edge of the integrated circuit. A volume may be determined by the I/O cell edge and the predetermined distance and one or more rails may be disposed in the volume and in at least one metal layer common with at least one metal layer of the bond pad. The rails may be involved in the discharge of electrostatic discharge (ESD) current, and may reduce path resistance of the path used to discharge the ESD current.
    Type: Application
    Filed: March 31, 2016
    Publication date: July 27, 2017
    Applicant: SanDisk Technologies Inc.
    Inventors: Shiv Harit Mathur, Anand Sharma, Lakhdar Iguelmamene, Richard Jk Hong, Rajeswara Rao Bandaru
  • Patent number: 9607058
    Abstract: The present disclosure relates to systems and methods for managing documents such as a prior art documents and documents for submission to government agencies such as an information disclosure statement (IDS) configured for submission to a patent office. In certain aspects, the system and methods include automatic retrieval of relevant documents, for example using a crawler service over a network such as the Internet. In certain aspects, the systems and methods include automatic optical character recognition and template matching to facilitate the extraction of information relating to certain documents. In certain aspects, the system and methods include a generating interface configured to present information to a generating user and to allow the generating user to select options relating to the citation of references in a particular patent family.
    Type: Grant
    Filed: May 20, 2016
    Date of Patent: March 28, 2017
    Assignee: BlackBox IP Corporation
    Inventors: Vivek Gupta, Amit Kumar Mohapatro, Anand Sharma, Amit Chauhan
  • Publication number: 20160365255
    Abstract: Ion implantation or deposition can be used to modify the bulk electrical properties of topological insulators. More particularly, ion implantation or deposition can be used to compensate for the non-zero bulk conductivity due to extrinsic charge carriers. The direct implantation of deposition/annealing of dopants allows better control over carrier concentrations for the purposes of achieving low bulk conductivity. Ion implantation or deposition enables the fabrication of inhomogeneously doped structures, enabling new types of device designs.
    Type: Application
    Filed: June 8, 2016
    Publication date: December 15, 2016
    Inventor: Peter Anand Sharma
  • Publication number: 20160191059
    Abstract: A transition tracking circuit may be configured to receive a first input signal and a second input signal from a level shifter. The transition tracking circuit may be configured to track earlier falling transitions of the first and second signals to generate an output signal.
    Type: Application
    Filed: March 24, 2015
    Publication date: June 30, 2016
    Inventors: Shiv Harit Mathur, Anand Sharma, Ramakrishnan Subramanian
  • Publication number: 20150379412
    Abstract: The present invention provides a forecasting engine with the ability to minimize prediction error in a preferred direction. It comprises of a receiver configured to receive training data samples. In addition, the forecasting engine includes a building module configured to build a base learner model from the training data samples. In addition, the forecasting engine includes a custom error function that emphasizes prediction error along a pre-configured direction. In addition, the forecasting engine includes an error determination module configured to determine the prediction error made by the base learner model. In addition, the forecasting engine includes an error minimization module configured to construct a new model that has lesser prediction error than the base learner model, where prediction error is as defined by the custom error function.
    Type: Application
    Filed: June 24, 2015
    Publication date: December 31, 2015
    Applicant: INMOBI PTE LTD.
    Inventors: Swaminathan Padmanabhan, Anand Sharma